Datasheet ADP5050 (Analog Devices)

5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator Data Sheet ADP5050 FEATURES TYPICAL APPLICATION CIRCUIT ADP5050 Wide input voltage range: 4.5 V to 15 V SYNC/MODE VREG ±1.5% output accuracy over full temperature range INT VREG VDD OSCILLATOR C1 100mA RT 250 kHz to 1.4 MHz adjustable switching frequency C0 FB1 PVIN1 Adjustable/fixed output options via factory fuse or I2C interface 4.5V TO 15V BST1 SW1 CHANNEL 1 C3 I2C interface with interrupt on fault conditions L1 C2 VOUT1 COMP1 BUCK REGULATOR (1.2A/2.5A/4A) Power regulation VREG C4 EN1 Q1 DL1 Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A SS12 R PGND ILIM1 sync buck regulators with low-side FET driver R DL2 ILIM2 Channel 3 and Channel 4: 1.2 A sync buck regulators Q2 PVIN2 C5 VREG Channel 5: 200 mA low dropout (LDO) regulator CHANNEL 2 SW2 VOUT2 BUCK REGULATOR COMP2 (1.2A/2.5A/4A) L2 Single 8 A output (Channel 1 and Channel 2 operated in parallel) C6 C7 BST2 EN2 FB2 Dynamic voltage scaling (DVS) for Channel 1 and Channel 4 Precision enable with 0.8 V accurate threshold PVIN3 BST3 Active output discharge switch C8 C9 L3 VOUT3 COMP3 CHANNEL 3 SW3 BUCK REGULATOR Programmable phase shift in 90° steps C10 (1.2A) FB3 EN3 Individual channel FPWM/PSM mode selection PGND3 SS34 Frequency synchronization input or output BST4 PVIN4 Optional latch-off protection on OVP/OCP failure C12 L4 SW4 VOUT4 CHANNEL 4 C11 BUCK REGULATOR Power-good flag on selected channels COMP4 FB4 C13 (1.2A) EN4 Low input voltage detection PGND4 1.7V TO 5.5V VOUT5 Overheat detection on junction temperature PVIN5 VOUT5 CHANNEL 5 EN5 200mA LDO C14 FB5 C15 UVLO, OCP, and TSD protection REGULATOR 48-lead, 7 mm × 7 mm LFCSP package VDDIO PWRGD I2C ALERT SCL INT −40°C to +125°C junction temperature SDA
01 0
APPLICATIONS
9-
EXPOSED PAD
89 10
Small cell base stations
Figure 1.
FPGA and processor applications Table 1. Family Models Security and surveillance Model Channels I2C Package Medical applications
ADP5050 Four bucks, one LDO Yes 48-Lead LFCSP
GENERAL DESCRIPTION
ADP5051 Four bucks, supervisory Yes 48-Lead LFCSP ADP5052 Four bucks, one LDO No 48-Lead LFCSP The ADP5050 combines four high performance buck regulators ADP5053 Four bucks, supervisory No 48-Lead LFCSP and one 200 mA low dropout (LDO) regulator in a 48-lead LFCSP ADP5054 Four high current bucks No 48-Lead LFCSP package that meets demanding performance and board space requirements. The device enables direct connection to high input The switching frequency of the ADP5050 can be programmed voltages up to 15 V with no preregulators. or synchronized to an external clock. The ADP5050 contains a precision enable pin on each channel for easy power-up sequencing Channel 1 and Channel 2 integrate high-side power MOSFETs and or adjustable UVLO threshold. low-side MOSFET drivers. External NFETs can be used in low-side power devices to achieve an efficiency optimized solution and The ADP5050 integrates a general-purpose LDO regulator with deliver a programmable output current of 1.2 A, 2.5 A, or 4 A. low quiescent current and low dropout voltage that provides up Combining Channel 1 and Channel 2 in a parallel configuration to 200 mA of output current. can provide a single output with up to 8 A of current. The optional I2C interface provides the user with flexible Channel 3 and Channel 4 integrate both high-side and low-side configuration options, including adjustable and fixed output MOSFETs to deliver output current of 1.2 A. voltage options, junction temperature overheat warning, low input voltage detection, and dynamic voltage scaling (DVS).
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS I2C INTERFACE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES DYNAMIC VOLTAGE SCALING (DVS) INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION INTERRUPT FUNCTION THERMAL SHUTDOWN OVERHEAT DETECTION LOW INPUT VOLTAGE DETECTION LDO REGULATOR I2C INTERFACE SDA AND SCL PINS I2C ADDRESSES SELF-CLEAR REGISTER BITS I2C INTERFACE TIMING DIAGRAMS APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS REGISTER MAP DETAILED REGISTER DESCRIPTIONS REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 REGISTER 2: VID1 (VID SETTING FOR CHANNEL 1), ADDRESS 0x02 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 REGISTER 4: VID4 (VID SETTING FOR CHANNEL 4), ADDRESS 0x04 REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C REGISTER 13: STATUS_RD (STATUS READBACK), ADDRESS 0x0D REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F REGISTER 17: DEFAULT_SET (DEFAULT RESET), ADDRESS 0x11 FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE