Datasheet ADP5050 (Analog Devices) - 5

Data Sheet ADP5050 SPECIFICATIONS
VIN = 12 V, VVREG = 5.1 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE VIN 4.5 15.0 V PVIN1, PVIN2, PVIN3, PVIN4 pins QUIESCENT CURRENT PVIN1, PVIN2, PVIN3, PVIN4 pins Operating Quiescent Current IQ(4-BUCKS) 4.8 6.25 mA No switching, all ENx pins high ISHDN(4BUCKS+LDO) 25 65 µA All ENx pins low UNDERVOLTAGE LOCKOUT UVLO PVIN1, PVIN2, PVIN3, PVIN4 pins Rising Threshold VUVLO-RISING 4.2 4.36 V Falling Threshold VUVLO-FALLING 3.6 3.78 V Hysteresis VHYS 0.42 V OSCILLATOR CIRCUIT Switching Frequency fSW 700 740 780 kHz RT = 25.5 kΩ Switching Frequency Range 250 1400 kHz SYNC Input Input Clock Range fSYNC 250 1400 kHz Input Clock Pulse Width Minimum On Time tSYNC_MIN_ON 100 ns Minimum Off Time tSYNC_MIN_OFF 100 ns Input Clock High Voltage VH(SYNC) 1.3 V Input Clock Low Voltage VL(SYNC) 0.4 V SYNC Output Clock Frequency fCLK fSW kHz Positive Pulse Duty Cycle tCLK_PULSE_DUTY 50 % Rise or Fall Time tCLK_RISE_FALL 10 ns High Level Voltage VH(SYNC_OUT) VVREG V PRECISION ENABLING EN1, EN2, EN3, EN4, EN5 pins High Level Threshold VTH_H(EN) 0.806 0.832 V Low Level Threshold VTH_L(EN) 0.688 0.725 V Pull-Down Resistor RPULL-DOWN(EN) 1.0 MΩ POWER GOOD Internal Power-Good Rising Threshold VPWRGD(RISE) 86.3 90.5 95 % Internal Power-Good Hysteresis VPWRGD(HYS) 3.3 % Internal Power-Good Falling Delay tPWRGD_FALL 50 µs Rising Delay for PWRGD Pin tPWRGD_PIN_RISE 1 ms Leakage Current for PWRGD Pin IPWRGD_LEAKAGE 0.1 1 µA Output Low Voltage for PWRGD Pin VPWRGD_LOW 50 100 mV IPWRGD = 1 mA LOGIC INPUTS (SCL AND SDA PINS) VDDIO = 3.3 V High Level Threshold VLOGIC_HIGH 0.7 × VDDIO V Low Level Threshold VLOGIC_LOW 0.3 × VDDIO V LOGIC OUTPUTS Low Level Output Voltage SDA Pin VSDA_LOW 0.4 V VDDIO = 3.3 V, ISDA = 3 mA INT Pin VINT_LOW 0.4 V IINT = 3 mA INTERNAL REGULATORS VDD Output Voltage VVDD 3.2 3.305 3.4 V IVDD = 10 mA VDD Current Limit ILIM_VDD 20 51 80 mA VREG Output Voltage VVREG 4.9 5.1 5.3 V VREG Dropout Voltage VDROPOUT 225 mV IVREG = 50 mA VREG Current Limit ILIM_VREG 50 95 140 mA Rev. C | Page 5 of 55 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS I2C INTERFACE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES DYNAMIC VOLTAGE SCALING (DVS) INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION INTERRUPT FUNCTION THERMAL SHUTDOWN OVERHEAT DETECTION LOW INPUT VOLTAGE DETECTION LDO REGULATOR I2C INTERFACE SDA AND SCL PINS I2C ADDRESSES SELF-CLEAR REGISTER BITS I2C INTERFACE TIMING DIAGRAMS APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS REGISTER MAP DETAILED REGISTER DESCRIPTIONS REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 REGISTER 2: VID1 (VID SETTING FOR CHANNEL 1), ADDRESS 0x02 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 REGISTER 4: VID4 (VID SETTING FOR CHANNEL 4), ADDRESS 0x04 REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C REGISTER 13: STATUS_RD (STATUS READBACK), ADDRESS 0x0D REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F REGISTER 17: DEFAULT_SET (DEFAULT RESET), ADDRESS 0x11 FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE