Datasheet ADP5050 (Analog Devices) - 4

ADP5050 Data Sheet DETAILED FUNCTIONAL BLOCK DIAGRAM CHANNEL 1 BUCK REGULATOR UVLO1 PVIN1 0.8V – + EN1 + ACS1 – 1MΩ VREG HICCUP + BST1 AND CLK1 OCP – LATCH-OFF Q1 DRIVER SLOPE COMP + SW1 CMP1 Q E DG1 CONTROL LOGIC H COMP1 – C AND MOSFET VREG IT DRIVER WITH CHARG W 0.8V + CLK1 S S EA1 ANTICROSS DI – DRIVER FB1 PROTECTION DL1 FREQUENCY PGND FOLDBACK ZERO OVP CROSS + LATCH-OFF VID1 – + 0.99V CURRENT-LIMIT 0.72V – PWRGD1 SELECTION CURRENT BALANCE PVIN2 EN2 CHANNEL 2 BUCK REGULATOR BST2 COMP2 DUPLICATE CHANNEL 1 DL2 FB2 SW2 VREG PVIN1 RT VREG OSCILLATOR INTERNAL REGULATOR SYNC/MODE VDD POWER-ON VDDIO SS12 I2C SOFT START HOUSEKEEPING RESET INTERFACE DECODER SCL LOGIC AND SS34 REGISTERS SDA PWRGD Q INT PWRGD CHANNEL 3 BUCK REGULATOR UVLO3 PVIN3 0.8V – + EN3 + ACS3 – 1MΩ VREG HICCUP + BST3 AND CLK3 OCP – LATCH-OFF Q3 DRIVER SLOPE COMP + CMP3 SW3 CONTROL LOGIC COMP3 – AND MOSFET VREG DRIVER WITH Q4 0.8V + CLK3 EA3 ANTICROSS DRIVER FB3 – PROTECTION FREQUENCY PGND3 FOLDBACK OVP ZERO + LATCH-OFF CROSS E H VID3 – C + 0.99V IT CHARG W – Q S S 0.72V PWRGD3 DG3 DI EN4 CHANNEL 4 BUCK REGULATOR PVIN4 BST4 DUPLICATE CHANNEL 3 COMP4 SW4 FB4 PGND4 CHANNEL 5 LDO REGULATOR PVIN5 VOUT5 0.8V – LDO Q7 – 0.5V CONTROL EN5 + EA5+ FB5 1MΩ
202 10899- Figure 2. Rev. C | Page 4 of 55 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS I2C INTERFACE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES DYNAMIC VOLTAGE SCALING (DVS) INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION INTERRUPT FUNCTION THERMAL SHUTDOWN OVERHEAT DETECTION LOW INPUT VOLTAGE DETECTION LDO REGULATOR I2C INTERFACE SDA AND SCL PINS I2C ADDRESSES SELF-CLEAR REGISTER BITS I2C INTERFACE TIMING DIAGRAMS APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS REGISTER MAP DETAILED REGISTER DESCRIPTIONS REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 REGISTER 2: VID1 (VID SETTING FOR CHANNEL 1), ADDRESS 0x02 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 REGISTER 4: VID4 (VID SETTING FOR CHANNEL 4), ADDRESS 0x04 REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C REGISTER 13: STATUS_RD (STATUS READBACK), ADDRESS 0x0D REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F REGISTER 17: DEFAULT_SET (DEFAULT RESET), ADDRESS 0x11 FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE