Datasheet ADP5020 (Analog Devices) - 9

ADP5020 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 D 1 2 N 1 D D 2 G W D D W P S V V S 1 2 1 D 6 7 8 9 0 2 1 N 1 1 1 1 2 D D W D D W G S V V S P 0 9 8 7 6 2 1 1 1 1 VOUT1 15 1 PGND2 PIN 1 VOUT1 14 ADP5020 2 VOUT2 PGND2 INDICATOR 1 15 VOUT1 VDD3 13 BOTTOM VIEW 3 VDDA (Not to Scale) VOUT2 2 14 VOUT1 VOUT3 12 4 AGND ADP5020 VDDA 3 13 VDD3 EN/GPIO 11 5 SYNC EXPOSED PAD TOP VIEW AGND 4 (Not to Scale) 12 VOUT3 SYNC 5 11 EN/GPIO 0 8 7 6 1 9 N O L A D D I C D N 6 7 8 9 0 T _ S S 1 H D G S D D D A L O N X V N D C I_ D
4
NOTES G S S T D
05 00
D H D
0 4-
1. EXPOSED PAD SHOULD BE CONNECTED S V
4- 77
X TO PGND1 AND PGND2.
77 07 07 Figure 4. Pin Configuration (Bottom View) Figure 5. Pin Configuration (Top View)
Table 9. Pin Function Descriptions Pin No. Mnemonic Description
1 PGND2 Power Ground Buck 2. 2 VOUT2 Feedback Buck 2. 3 VDDA Supply Voltage Internal Analog Circuit. 4 AGND Analog Ground. 5 SYNC Frequency Synchronization. Connect to an external 19.2 MHz or 9.6 MHz clock signal to synchronize the internal oscillator. 6 DGND Digital Ground. 7 SDA I2C Data. 8 SCL I2C Clock. 9 VDD_IO Supply Voltage for Internal Logic Inputs/Outputs. 10 XSHTDN Shutdown Output, Active Low. 11 EN/GPIO After power-on reset, this pin is defined as enable (EN). To enable active high, the I2C command can program this pin to be an output (GPIO). A weak pull-down resistor is enabled when the pin operates as EN. 12 VOUT3 Regulated Output Voltage from LDO. 13 VDD3 Supply Voltage LDO. 14, 15 VOUT1 Feedback/Driver Buck 1 Output. 16 PGND1 Power Ground Buck 1. 17 SW1 Switch Pin Buck 1. 18 VDD1 Supply Voltage Buck 1. 19 VDD2 Supply Voltage Buck 2. 20 SW2 Switch Pin Buck 2. EPAD Exposed paddle Exposed pad should be connected to PGND1 and PGND2. Rev. 0 | Page 9 of 28 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATIONS CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS SWITCHING SPECIFICATIONS DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR VOUT3 SPECIFICATIONS, LOW DROPOUT (LDO) REGULATOR I2C TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Thermal Data ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT OPERATION INTERNAL COMPENSATION CURRENT LIMITING AND SHORT-CIRCUIT PROTECTION SYNCHRONIZATION I2C INTERFACE UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN CONTROL REGISTERS DEVICE ADDRESS REGISTER MAP REGISTER DESCRIPTIONS User Accessible Registers POWER-UP/POWER-DOWN SEQUENCE SEQUENCER DEFAULT POWER-ON SEQUENCE WITH EN PIN Activation Waveforms POWER-ON SEQUENCE USING THE I2C INTERFACE POWER-UP/POWER-DOWN STATE FLOW APPLICATIONS INFORMATION POWER GOOD STATUS XSHTDN LOGIC COMPONENTS SELECTION Buck Inductor Input Capacitor Selection Output Capacitor Selection LDO INPUT FILTER LAYOUT RECOMMENDATIONS APPLICATIONS SCHEMATIC PCB BOARD LAYOUT RECOMMENDATIONS EXTERNAL COMPONENT LIST OUTLINE DIMENSIONS ORDERING GUIDE