Datasheet ADSP-BF539, ADSP-BF539F (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | Blackfin Embedded Processor |
| 页数 / 页 | 60 / 2 — ADSP-BF539/. ADSP-BF539F. TABLE OF CONTENTS. REVISION HISTORY. 10/13—Rev. … |
| 修订版 | F |
| 文件格式/大小 | PDF / 2.5 Mb |
| 文件语言 | 英语 |
ADSP-BF539/. ADSP-BF539F. TABLE OF CONTENTS. REVISION HISTORY. 10/13—Rev. E to Rev. F
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ADSP-BF539/ ADSP-BF539F TABLE OF CONTENTS
Features ... 1 Booting Modes ... 16 Memory .. 1 Instruction Set Description .. 17 Peripherals ... 1 Development Tools .. 17 General Description ... 3 Example Connections and Layout Considerations ... 18 Low Power Architecture ... 3 MXVR Board Layout Guidelines ... 18 System Integration .. 3 Voltage Regulator Layout Guidelines ... 19 ADSP-BF539/ADSP-BF539F Processor Peripherals ... 3 Additional Information .. 20 Blackfin Processor Core .. 4 Related Signal Chains ... 20 Memory Architecture .. 5 Pin Descriptions .. 21 DMA Controllers .. 8 Specifications .. 26 Real-Time Clock ... 9 Operating Conditions ... 26 Watchdog Timer .. 9 Electrical Characteristics ... 27 Timers ... 9 Absolute Maximum Ratings ... 30 Serial Ports (SPORTs) .. 10 ESD Sensitivity ... 30 Serial Peripheral Interface (SPI) Ports .. 10 Package Information .. 30 2-Wire Interface ... 10 Timing Specifications ... 31 UART Ports .. 10 Output Drive Currents ... 50 Programmable I/O Pins .. 11 Test Conditions .. 52 Parallel Peripheral Interface ... 12 Thermal Characteristics .. 55 Controller Area Network (CAN) Interface .. 12 316-Ball CSP_BGA Ball Assignment ... 56 Media Transceiver MAC layer (MXVR) ... 13 Outline Dimensions .. 59 Dynamic Power Management .. 13 Surface-Mount Design .. 59 Voltage Regulation .. 15 Ordering Guide ... 60 Clock Signals ... 15
REVISION HISTORY 10/13—Rev. E to Rev. F
Updated Development Tools .. 17 Added notes to Table 32 in Serial Ports—Enable and Three-State .. 43 Added Timer Clock Timing .. 48 Revised Timer Cycle Timing ... 48 To view product/process change notifications (PCNs) related to this data sheet revision, please visit the processor’s product page on the www.analog.com website and use the View PCN link. Rev. F | Page 2 of 60 | October 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF539/ADSP-BF539F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF539F Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports Programmable I/O Pins Programmable Flags (GPIO Port F) General-Purpose I/O Ports C, D, and E Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Media Transceiver MAC layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Example Connections and Layout Considerations MXVR Board Layout Guidelines Voltage Regulator Layout Guidelines Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing MXVR Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide
ADSP-BF539/ ADSP-BF539F TABLE OF CONTENTS
Features ... 1 Booting Modes ... 16 Memory .. 1 Instruction Set Description .. 17 Peripherals ... 1 Development Tools .. 17 General Description ... 3 Example Connections and Layout Considerations ... 18 Low Power Architecture ... 3 MXVR Board Layout Guidelines ... 18 System Integration .. 3 Voltage Regulator Layout Guidelines ... 19 ADSP-BF539/ADSP-BF539F Processor Peripherals ... 3 Additional Information .. 20 Blackfin Processor Core .. 4 Related Signal Chains ... 20 Memory Architecture .. 5 Pin Descriptions .. 21 DMA Controllers .. 8 Specifications .. 26 Real-Time Clock ... 9 Operating Conditions ... 26 Watchdog Timer .. 9 Electrical Characteristics ... 27 Timers ... 9 Absolute Maximum Ratings ... 30 Serial Ports (SPORTs) .. 10 ESD Sensitivity ... 30 Serial Peripheral Interface (SPI) Ports .. 10 Package Information .. 30 2-Wire Interface ... 10 Timing Specifications ... 31 UART Ports .. 10 Output Drive Currents ... 50 Programmable I/O Pins .. 11 Test Conditions .. 52 Parallel Peripheral Interface ... 12 Thermal Characteristics .. 55 Controller Area Network (CAN) Interface .. 12 316-Ball CSP_BGA Ball Assignment ... 56 Media Transceiver MAC layer (MXVR) ... 13 Outline Dimensions .. 59 Dynamic Power Management .. 13 Surface-Mount Design .. 59 Voltage Regulation .. 15 Ordering Guide ... 60 Clock Signals ... 15
REVISION HISTORY 10/13—Rev. E to Rev. F
Updated Development Tools .. 17 Added notes to Table 32 in Serial Ports—Enable and Three-State .. 43 Added Timer Clock Timing .. 48 Revised Timer Cycle Timing ... 48 To view product/process change notifications (PCNs) related to this data sheet revision, please visit the processor’s product page on the www.analog.com website and use the View PCN link. Rev. F | Page 2 of 60 | October 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF539/ADSP-BF539F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF539F Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports Programmable I/O Pins Programmable Flags (GPIO Port F) General-Purpose I/O Ports C, D, and E Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Media Transceiver MAC layer (MXVR) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Example Connections and Layout Considerations MXVR Board Layout Guidelines Voltage Regulator Layout Guidelines Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing MXVR Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide