Datasheet ADN2805 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 1.25 Gbps Clock and Data Recovery IC |
| 页数 / 页 | 16 / 7 — Data Sheet. ADN2805. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. 26 CL. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 293 Kb |
| 文件语言 | 英语 |
Data Sheet. ADN2805. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. 26 CL. 25 CL. VCC 1. PIN 1. 24 VCC. VCC 2. INDIC ATOR. 23 VEE. VREF 3. 22 NC
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Data Sheet ADN2805 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS P N T T H P N U U C O O L UT UT E C C E TA TA U KO KO A A VC VC VE D D SQ 32 31 30 29 28 27 26 CL 25 CL VCC 1 PIN 1 24 VCC VCC 2 INDIC ATOR 23 VEE VREF 3 22 NC NIN 4 ADN2805* 21 SDA PIN 5 TOP VIEW 20 SCK NC 6 (Not to Scale) 19 SADDR5 NC 7 18 VCC VEE 8 17 VEE 0 11 2 3 6 1 1 1 P 1 N C 2 14 1 15 L NC 9 K L LK VC VEE CF CF LO C F FC E RE R
5
* THERE IS AN EXPOSED PAD ON THE BOTTOM OF
00 1-
THE PACKAGE THAT MUST BE CONNECTED TO GND.
12 07 Figure 5. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1 VCC AI Connect to VCC. 2 VCC P Power for Limiting Amplifier, LOS. 3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor. 4 NIN AI Differential Data Input. CML. 5 PIN AI Differential Data Input. CML. 6, 7, 9, 22 NC No Connect. 8 VEE P GND for Limiting Amplifier, LOS. 10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz. 11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz. 12 VCC P VCO Power. 13 VEE P VCO GND. 14 CF2 AO Frequency Loop Capacitor. 15 CF1 AO Frequency Loop Capacitor. 16 LOL DO Loss-of-Lock Indicator. LVTTL active high. 17 VEE P FLL Detector GND. 18 VCC P FLL Detector Power. 19 SADDR5 DI Slave Address Bit 5. 20 SCK DI I2C Clock Input. 21 SDA DI I2C Data Input. 23 VEE P Output Buffer, I2C GND. 24 VCC P Output Buffer, I2C Power. 25 CLKOUTN DO Differential Recovered Clock Output. LVDS. 26 CLKOUTP DO Differential Recovered Clock Output. LVDS. 27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL. 28 DATAOUTN DO Differential Recovered Data Output. LVDS. 29 DATAOUTP DO Differential Recovered Data Output. LVDS. 30 VEE P Phase Detector, Phase Shifter GND. 31 VCC P Phase Detector, Phase Shifter Power. 32 VCC AI Connect to VCC. Exposed Pad Pad P Connect to GND. Works as a heat sink. 1 Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output. Rev. B | Page 7 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS JITTER SPECIFICATIONS OUTPUT AND TIMING SPECIFICATIONS Timing Characteristics ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Thermal Resistance ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION INPUT BUFFER LOCK DETECTOR OPERATION Normal Mode LOL Detector Operation Using a Reference Clock Static LOL Mode SQUELCH MODE SYSTEM RESET I2C INTERFACE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADN2805 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS P N T T H P N U U C O O L UT UT E C C E TA TA U KO KO A A VC VC VE D D SQ 32 31 30 29 28 27 26 CL 25 CL VCC 1 PIN 1 24 VCC VCC 2 INDIC ATOR 23 VEE VREF 3 22 NC NIN 4 ADN2805* 21 SDA PIN 5 TOP VIEW 20 SCK NC 6 (Not to Scale) 19 SADDR5 NC 7 18 VCC VEE 8 17 VEE 0 11 2 3 6 1 1 1 P 1 N C 2 14 1 15 L NC 9 K L LK VC VEE CF CF LO C F FC E RE R
5
* THERE IS AN EXPOSED PAD ON THE BOTTOM OF
00 1-
THE PACKAGE THAT MUST BE CONNECTED TO GND.
12 07 Figure 5. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1 VCC AI Connect to VCC. 2 VCC P Power for Limiting Amplifier, LOS. 3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor. 4 NIN AI Differential Data Input. CML. 5 PIN AI Differential Data Input. CML. 6, 7, 9, 22 NC No Connect. 8 VEE P GND for Limiting Amplifier, LOS. 10 REFCLKP DI Differential REFCLK Input. 10 MHz to 160 MHz. 11 REFCLKN DI Differential REFCLK Input. 10 MHz to 160 MHz. 12 VCC P VCO Power. 13 VEE P VCO GND. 14 CF2 AO Frequency Loop Capacitor. 15 CF1 AO Frequency Loop Capacitor. 16 LOL DO Loss-of-Lock Indicator. LVTTL active high. 17 VEE P FLL Detector GND. 18 VCC P FLL Detector Power. 19 SADDR5 DI Slave Address Bit 5. 20 SCK DI I2C Clock Input. 21 SDA DI I2C Data Input. 23 VEE P Output Buffer, I2C GND. 24 VCC P Output Buffer, I2C Power. 25 CLKOUTN DO Differential Recovered Clock Output. LVDS. 26 CLKOUTP DO Differential Recovered Clock Output. LVDS. 27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTTL. 28 DATAOUTN DO Differential Recovered Data Output. LVDS. 29 DATAOUTP DO Differential Recovered Data Output. LVDS. 30 VEE P Phase Detector, Phase Shifter GND. 31 VCC P Phase Detector, Phase Shifter Power. 32 VCC AI Connect to VCC. Exposed Pad Pad P Connect to GND. Works as a heat sink. 1 Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output. Rev. B | Page 7 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS JITTER SPECIFICATIONS OUTPUT AND TIMING SPECIFICATIONS Timing Characteristics ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Thermal Resistance ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION INPUT BUFFER LOCK DETECTOR OPERATION Normal Mode LOL Detector Operation Using a Reference Clock Static LOL Mode SQUELCH MODE SYSTEM RESET I2C INTERFACE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE