Datasheet ADN2805 (Analog Devices) - 8

ADN2805 Data Sheet I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION R/W SLAVE ADDRESS [6...0] CTRL. 1 A5 0 0 0 0 0 X
06
MSB = 1 SET BY 0 = WR
0 1-
PIN 19 1 = RD
12 07 Figure 6. Slave Address Configuration 7 00
S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P
21- 071 Figure 7. I2C Write Data Transfer
S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) S SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M) DATA A(M) P
08
S = START BIT P = STOP BIT A(M) = LACK OF ACKNOWLEDGE BY MASTER
-0 21
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
71 0 Figure 8. I2C Read Data Transfer
START BIT STOP BIT SLAVE ADDRESS SUB ADDRESS DATA SDA A6 A5 A7 A0 D7 D0 SCK S WR ACK ACK ACK P
009
SLADDR[4...0] SUB ADDR[6...1] DATA[6...1]
121- 07 Figure 9. I2C Data Transfer Timing
tF tSU;DAT tHD;STA t SDA BUF tR t t R tF SU;STO tLOW SCK t t HD;STA HIGH tSU;STA
0 01
S S t
1-
P S HD;DAT
12 07 Figure 10. I2C Port Timing Diagram Rev. B | Page 8 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS JITTER SPECIFICATIONS OUTPUT AND TIMING SPECIFICATIONS Timing Characteristics ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Thermal Resistance ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION INPUT BUFFER LOCK DETECTOR OPERATION Normal Mode LOL Detector Operation Using a Reference Clock Static LOL Mode SQUELCH MODE SYSTEM RESET I2C INTERFACE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE