Datasheet ADN2805 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | 1.25 Gbps Clock and Data Recovery IC |
| 页数 / 页 | 16 / 9 — Data Sheet. ADN2805. Table 7. Internal Register Map1, 2. Reg. Name. R/W. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 293 Kb |
| 文件语言 | 英语 |
Data Sheet. ADN2805. Table 7. Internal Register Map1, 2. Reg. Name. R/W. Address. D7 D6 D5 D4. D3 D2
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Data Sheet ADN2805 Table 7. Internal Register Map1, 2 Reg. Name R/W Address D7 D6 D5 D4 D3 D2 D1 D0
FREQ0 R 0x0 MSB LSB FREQ1 R 0x1 MSB LSB FREQ2 R 0x2 0 MSB LSB RATE R 0x3 COARSE_RD[8] MSB Coarse Data Rate Readback COARSE_RD[1] MISC R 0x4 X X X Static LOL Data Rate X COARSE_RD[0] LOL Status Measure (LSB) Complete CTRLA W 0x8 fREF Range Data Rate/DIV_fREF Ratio Measure Data Rate Lock to Reference CTRLB W 0x9 Config Reset System 0 Reset 0 0 0 LOL MISC[4] Reset MISC[2] CTRLC W 0x11 0 0 0 0 0 0 Squelch Mode Output Boost 1 All writeable registers default to 0x00. 2 X = don’t care.
Table 8. Miscellaneous Register, MISC1 Static LOL LOL Status Data Rate Measurement Complete Coarse Rate Readback LSB D7 D6 D5 D4 D3 D2 D1 D0
X X X 0 = waiting for next LOL 0 = locked 0 = measuring data rate X COARSE_RD[0] 1 = static LOL until reset 1 = acquiring 1 = measurement complete 1 X = don’t care.
Table 9. Control Register, CTRLA1 fREF Range Data Rate/DIV_fREF Ratio Measure Data Rate Lock to Reference D7 D6 D5 D4 D3 D2 D1 D0
0 0 10 MHz to 20 MHz 0 0 0 0 1 Set to 1 to measure data rate 0 = lock to input data 0 1 20 MHz to 40 MHz 0 0 0 1 2 1 = lock to reference clock 1 0 40 MHz to 80 MHz 0 0 1 0 4 1 1 80 MHz to 160 MHz n 2n 1 0 0 0 256 1 Where DIV_fREF is the divided down reference referred to the 10 MHz to 20 MHz band.
Table 10. Control Register, CTRLB Configure LOL Reset MISC[4] System Reset Reset MISC[2] D7 D6 D5 D4 D3 D2 D1 D0
0 = LOL pin normal operation Write a 1 followed by Write a 1 followed by Set to 0 Write a 1 followed by Set to 0 Set to 0 Set to 0 1 = LOL pin is static LOL 0 to reset MISC[4] 0 to reset ADN2805 0 to reset MISC[2]
Table 11. Control Register, CTRLC Squelch Mode Output Boost D7 D6 D5 D4 D3 D2 D1 D0
Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 0 = SQUELCH DATAOUT and CLKOUT 0 = default output swing 1 = SQUELCH DATAOUT or CLKOUT 1 = boost output swing Rev. B | Page 9 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS JITTER SPECIFICATIONS OUTPUT AND TIMING SPECIFICATIONS Timing Characteristics ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Thermal Resistance ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION INPUT BUFFER LOCK DETECTOR OPERATION Normal Mode LOL Detector Operation Using a Reference Clock Static LOL Mode SQUELCH MODE SYSTEM RESET I2C INTERFACE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADN2805 Table 7. Internal Register Map1, 2 Reg. Name R/W Address D7 D6 D5 D4 D3 D2 D1 D0
FREQ0 R 0x0 MSB LSB FREQ1 R 0x1 MSB LSB FREQ2 R 0x2 0 MSB LSB RATE R 0x3 COARSE_RD[8] MSB Coarse Data Rate Readback COARSE_RD[1] MISC R 0x4 X X X Static LOL Data Rate X COARSE_RD[0] LOL Status Measure (LSB) Complete CTRLA W 0x8 fREF Range Data Rate/DIV_fREF Ratio Measure Data Rate Lock to Reference CTRLB W 0x9 Config Reset System 0 Reset 0 0 0 LOL MISC[4] Reset MISC[2] CTRLC W 0x11 0 0 0 0 0 0 Squelch Mode Output Boost 1 All writeable registers default to 0x00. 2 X = don’t care.
Table 8. Miscellaneous Register, MISC1 Static LOL LOL Status Data Rate Measurement Complete Coarse Rate Readback LSB D7 D6 D5 D4 D3 D2 D1 D0
X X X 0 = waiting for next LOL 0 = locked 0 = measuring data rate X COARSE_RD[0] 1 = static LOL until reset 1 = acquiring 1 = measurement complete 1 X = don’t care.
Table 9. Control Register, CTRLA1 fREF Range Data Rate/DIV_fREF Ratio Measure Data Rate Lock to Reference D7 D6 D5 D4 D3 D2 D1 D0
0 0 10 MHz to 20 MHz 0 0 0 0 1 Set to 1 to measure data rate 0 = lock to input data 0 1 20 MHz to 40 MHz 0 0 0 1 2 1 = lock to reference clock 1 0 40 MHz to 80 MHz 0 0 1 0 4 1 1 80 MHz to 160 MHz n 2n 1 0 0 0 256 1 Where DIV_fREF is the divided down reference referred to the 10 MHz to 20 MHz band.
Table 10. Control Register, CTRLB Configure LOL Reset MISC[4] System Reset Reset MISC[2] D7 D6 D5 D4 D3 D2 D1 D0
0 = LOL pin normal operation Write a 1 followed by Write a 1 followed by Set to 0 Write a 1 followed by Set to 0 Set to 0 Set to 0 1 = LOL pin is static LOL 0 to reset MISC[4] 0 to reset ADN2805 0 to reset MISC[2]
Table 11. Control Register, CTRLC Squelch Mode Output Boost D7 D6 D5 D4 D3 D2 D1 D0
Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 0 = SQUELCH DATAOUT and CLKOUT 0 = default output swing 1 = SQUELCH DATAOUT or CLKOUT 1 = boost output swing Rev. B | Page 9 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS JITTER SPECIFICATIONS OUTPUT AND TIMING SPECIFICATIONS Timing Characteristics ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Thermal Resistance ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION THEORY OF OPERATION FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION INPUT BUFFER LOCK DETECTOR OPERATION Normal Mode LOL Detector Operation Using a Reference Clock Static LOL Mode SQUELCH MODE SYSTEM RESET I2C INTERFACE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes Transmission Lines Soldering Guidelines for Lead Frame Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE