数据表Datasheet AD8285 (Analog Devices)
Datasheet AD8285 (Analog Devices)
制造商 | Analog Devices |
描述 | Radar Receive Path AFE: 4-Channel LNA/PGA/AAF with ADC |
页数 / 页 | 27 / 1 — Radar Receive Path AFE: 4-Channel. LNA/PGA/AAF with ADC. Data Sheet. … |
修订版 | B |
文件格式/大小 | PDF / 511 Kb |
文件语言 | 英语 |
Radar Receive Path AFE: 4-Channel. LNA/PGA/AAF with ADC. Data Sheet. AD8285. FEATURES. FUNCTIONAL BLOCK DIAGRAM
该数据表的模型线
文件文字版本
Radar Receive Path AFE: 4-Channel LNA/PGA/AAF with ADC Data Sheet AD8285 FEATURES FUNCTIONAL BLOCK DIAGRAM x x x x 4-channel LNA, PGA, and AAF 8 3 8 3 N D1 D3 S D1 D3 D D W XA D D EF IA 1 direct to ADC channel SEL Z AV AV PD MU DV DV VR RB Programmable gain amplifier (PGA) Includes low noise preamplifier (LNA) INA+ REFERENCE LNA PGA INA– AAF Serial peripheral interface (SPI) programmable gain 16 dB to 34 dB in 6 dB steps INB+ LNA PGA INB– AAF Antialiasing filter (AAF) DSYNC MUX INC+ Programmable third order, low-pass elliptic filter (LPF) LNA PGA AAF INC– 12-BIT from 1.0 MHz to 12.0 MHz DRV D[0:11] ADC IND+ LNA PGA AAF Analog-to-digital converter (ADC) IND– 12 bits of accuracy up to 72 MSPS INADC+ INADC– Signal-to-noise ratio (SNR): 68.5 dB SPI Spurious-free dynamic range (SFDR): 68 dB at gain = 16 dB AD8285 Low power: 185 mW per channel at 12 bits and 72 MSPS Low noise: 3.5 nV/√Hz maximum of input referred voltage noise K X CS L IO K+ K– AU SC SD CL CL Power-down mode NOTES
1
72-lead, 10 mm × 10 mm LFCSP package 1. AVDD18x = AVDD18, AVDD18ADC.
00
AVDD33x = AVDD33, AVDD33A, AVDD33B, AVDD33C, AVDD33D, AVDD33REF.
2-
Specified from −40°C to +105°C DVDD18x = DVDD18, DVDD18CLK. DVDD33x = DVDD33, DVDD33SPI, DVDD33CLK, DVDD33DRV.
195 1
Qualified for automotive applications
Figure 1.
APPLICATIONS Automotive radar Adaptive cruise control Collision avoidance Blind spot detection Self parking Electronic bumper GENERAL DESCRIPTION
The AD8285 is designed for low cost, low power, compact size, Fabricated in an advanced complementary metal oxide flexibility, and ease of use. It contains four channels of a low noise semiconductor (CMOS) process, the AD8285 is available in a preamplifier (LNA) with a programmable gain amplifier (PGA) 10 mm × 10 mm, RoHS compliant, 72-lead LFCSP that is specified and an antialiasing filter (AAF) plus one direct to ADC channel, all over the automotive temperature range of −40°C to +105°C. integrated with a single 12-bit analog-to-digital converter (ADC).
Table 1. Related Devices
Each channel features a gain range of 16 dB to 34 dB in 6 dB
Part No. Description
increments and an ADC with a conversion rate of up to 72 MSPS. AD8283 6-channel LNA/PGA/AAF, pseudo simultaneous The combined input referred noise voltage of the entire channel channel sampling with ADC is 3.5 nV/√Hz at maximum gain. The channel is optimized for AD8284 4-channel LNA/PGA/AAF, sequential channel dynamic performance and low power in applications where a sampling with ADC small package size is critical. ADA8282 4-channel LNA/PGA
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Antialiasing Filter (AAF) Mux and Mux Controller ADC CLOCK INPUT CONSIDERATIONS CLOCK DUTY CYCLE CONSIDERATIONS CLOCK JITTER CONSIDERATIONS SDIO PIN SCLK PIN CS\ PIN RBIAS PIN VOLTAGE REFERENCE POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS SERIAL PERIPHERAL INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE LOGIC LEVELS RESERVED LOCATIONS DEFAULT VALUES APPLICATION DIAGRAMS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS