Datasheet AD8285 (Analog Devices) - 6
| 制造商 | Analog Devices |
| 描述 | Radar Receive Path AFE: 4-Channel LNA/PGA/AAF with ADC |
| 页数 / 页 | 27 / 6 — AD8285. Data Sheet. SWITCHING SPECIFICATIONS. Table 4. Parameter2 … |
| 修订版 | B |
| 文件格式/大小 | PDF / 511 Kb |
| 文件语言 | 英语 |
AD8285. Data Sheet. SWITCHING SPECIFICATIONS. Table 4. Parameter2 Temperature. Min. Typ. Max. Unit. N –1. INAx. tEH. tEL. CLK–. CLK+. D[11:0]. N – 7
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AD8285 Data Sheet SWITCHING SPECIFICATIONS
AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI = DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted.
Table 4. Parameter2 Temperature Min Typ Max Unit
CLOCK Clock Rate Full 10 72 MSPS Clock Pulse Width High (tEH) at 72 MSPS Full 6.94 ns Clock Pulse Width Low (tEL) at 72 MSPS Full 6.94 ns Clock Pulse Width High (tEH) at 40 MSPS Full 12.5 ns Clock Pulse Width Low (tEL) at 40 MSPS Full 12.5 ns OUTPUT PARAMETERS Propagation Delay (tPD) at 72 MSPS Full 1.5 2.5 5.0 ns Rise Time (tR)3 Full 1.9 ns Fall Time (tF)3 Full 1.2 ns Data Set-Up Time (tDS) at 72 MSPS Full 9.0 10.0 11.0 ns Data Hold Time (tDH) at 72 MSPS Full 1.5 4.0 5.0 ns Data Set-Up Time (tDS) at 40 MSPS Full 21.5 22.5 23.5 ns Data Hold Time (tDH) at 40 MSPS Full 1.5 4.0 5.0 ns Pipeline Latency Full 7 Clock cycles 1 x stands for A, B, C, or D. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions, and how these tests were completed. 3 Not shown in Figure 2.
N N –1 INAx tEH tEL CLK– CLK+ t t t PD DS DH D[11:0] N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N
-002 1952 1 Figure 2. Timing Definitions for Switching Specifications Rev. B | Page 6 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Antialiasing Filter (AAF) Mux and Mux Controller ADC CLOCK INPUT CONSIDERATIONS CLOCK DUTY CYCLE CONSIDERATIONS CLOCK JITTER CONSIDERATIONS SDIO PIN SCLK PIN CS\ PIN RBIAS PIN VOLTAGE REFERENCE POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS SERIAL PERIPHERAL INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE LOGIC LEVELS RESERVED LOCATIONS DEFAULT VALUES APPLICATION DIAGRAMS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
AD8285 Data Sheet SWITCHING SPECIFICATIONS
AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI = DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted.
Table 4. Parameter2 Temperature Min Typ Max Unit
CLOCK Clock Rate Full 10 72 MSPS Clock Pulse Width High (tEH) at 72 MSPS Full 6.94 ns Clock Pulse Width Low (tEL) at 72 MSPS Full 6.94 ns Clock Pulse Width High (tEH) at 40 MSPS Full 12.5 ns Clock Pulse Width Low (tEL) at 40 MSPS Full 12.5 ns OUTPUT PARAMETERS Propagation Delay (tPD) at 72 MSPS Full 1.5 2.5 5.0 ns Rise Time (tR)3 Full 1.9 ns Fall Time (tF)3 Full 1.2 ns Data Set-Up Time (tDS) at 72 MSPS Full 9.0 10.0 11.0 ns Data Hold Time (tDH) at 72 MSPS Full 1.5 4.0 5.0 ns Data Set-Up Time (tDS) at 40 MSPS Full 21.5 22.5 23.5 ns Data Hold Time (tDH) at 40 MSPS Full 1.5 4.0 5.0 ns Pipeline Latency Full 7 Clock cycles 1 x stands for A, B, C, or D. 2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions, and how these tests were completed. 3 Not shown in Figure 2.
N N –1 INAx tEH tEL CLK– CLK+ t t t PD DS DH D[11:0] N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1 N
-002 1952 1 Figure 2. Timing Definitions for Switching Specifications Rev. B | Page 6 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Antialiasing Filter (AAF) Mux and Mux Controller ADC CLOCK INPUT CONSIDERATIONS CLOCK DUTY CYCLE CONSIDERATIONS CLOCK JITTER CONSIDERATIONS SDIO PIN SCLK PIN CS\ PIN RBIAS PIN VOLTAGE REFERENCE POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS SERIAL PERIPHERAL INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE LOGIC LEVELS RESERVED LOCATIONS DEFAULT VALUES APPLICATION DIAGRAMS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS