Datasheet ADA8282 (Analog Devices) - 4

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ADA8282 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY Total Power Dissipation PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 73 mW PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 106 mW PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 139 mW PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 219 mW Power Dissipation per Channel 31 mW AVDD 3.0 3.6 V VIO 1.8 3.6 V IAVDD Four channels active PGA_BIAS_SEL = b’00, LNA_BIAS_SEL = b’00 19.6 22 mA PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’01 29 32 mA PGA_BIAS_SEL = b’01, LNA_BIAS_SEL = b’10 37.7 42 mA PGA_BIAS_SEL = b’11, LNA_BIAS_SEL = b’11 60 66.3 mA One channel active 9.8 11 mA IVIO 10 12 μA Power-Down Current IAVDD and IVIO 20 100 μA Power-Down Dissipation 0.07 0.33 mW Power-Up Time Time to operational after chip is enabled 5 μs Power Supply Rejection Ratio (PSRR) At dc −80 dB At 1 MHz −80 dB INPUT Input Resistance Differential Input Resistance 1.45 1.57 1.7 kΩ Common-Mode Input Resistance 0.37 0.39 0.42 kΩ Differential Input Capacitance 10.8 12 13.2 pF OUTPUT Output Voltage Swing +OUTx (−OUTx), gain = 18 dB 3.1 V p-p +OUTx (−OUTx), gain = 24 dB, 30 dB, or 36 dB 6.3 V p-p Output Balance fIN = 100 kHz −70 dB Short-Circuit Current Per output at 25°C 205 mA Capacitive Load 20% overshoot 30 pF 1 Normalized to 0° phase matching at 25°C; see the Theory of Operation section for details.
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, TA = −40°C to +125°C, unless otherwise noted.
Table 2. Parameter Temperature Min Typ Max Unit
LOGIC INPUT (CS) Logic 1 Voltage Full 1.2 VIO + 0.3 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 15 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUTS (SDI, SCLK, RESET) Logic 1 Voltage Full 1.2 VIO + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 2.5 kΩ Input Capacitance 25°C 2 pF Maximum SCLK Frequency 10 MHz LOGIC OUTPUT (SDO) Logic 1 Voltage (IOH = 800 μA) Full VIO − 0.3 V Logic 0 Voltage (IOL = 50 μA) Full 0.3 V Rev. 0 | Page 4 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS DIGITAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE DEFAULT SPI SETTINGS INPUT IMPEDANCE POWER MODES PROGRAMMABLE GAIN RANGE OUTPUT SWING VARIATION WITH GAIN OFFSET VOLTAGE ADJUSTMENTS VIO Pin SINGLE-ENDED OR DIFFERENTIAL INPUT SHORT-CIRCUIT CURRENTS SPI INTERFACE CHANNEL TO CHANNEL PHASE MATCHING APPLICATIONS INFORMATION INCREASED GAIN USING TWO ADA8282 DEVICES IN SERIES MULTIPLEXING INPUTS USING MULTIPLE ADA8282 DEVICES BASIC CONNECTIONS FOR A TYPICAL APPLICATION REGISTER MAP REGISTER SUMMARY REGISTER DETAILS Register 0x00: Interface Configuration Register Register 0x01: Soft Reset Register Register 0x04: Chip ID Low Register Register 0x05: Chip ID High Register Register 0x06: Revision Register Register 0x10: LNA Offset 0 Register Register 0x11: LNA Offset 1 Register Register 0x12: LNA Offset 2 Register Register 0x13: LNA Offset 3 Register Register 0x14: PGA Bias Register Register 0x15: PGA Gain Register Register 0x17: Enable Channel Register Register 0x18: Enable Bias Generator Register Register 0x1D: GPIO Write Register Register 0x1E: GPIO Read Register OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS