Datasheet ADA8282 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Radar Receive Path AFE: 4-Channel LNA and PGA |
| 页数 / 页 | 21 / 10 — ADA8282. Data Sheet. 120. GAIN = 18dB GAIN = 24dB GAIN = 30dB. –20. 100. … |
| 文件格式/大小 | PDF / 517 Kb |
| 文件语言 | 英语 |
ADA8282. Data Sheet. 120. GAIN = 18dB GAIN = 24dB GAIN = 30dB. –20. 100. GAIN = 36dB. –40. B) d. K (. –60. AL T. RR (. –80. CRO. –100. –120. –140. 10k. 100k
该数据表的模型线
文件文字版本
ADA8282 Data Sheet 120 0 GAIN = 18dB GAIN = 24dB GAIN = 30dB –20 100 GAIN = 36dB –40 80 B) d B) K ( –60 d 60 AL T RR ( S S S –80 P 40 CRO –100 20 –120 0 –140 10k 100k 1M 10M 100M
122
10k 100k 1M 10M 100M
124
FREQUENCY (Hz)
13132-
FREQUENCY (Hz)
13132- Figure 21. PSRR vs. Frequency at Various Gains Figure 23. Crosstalk vs. Frequency
100 37.85 90 37.80 80 70 mA) ( 37.75 60 B) NT d 50 37.70 RR ( CURRE CM 40 Y L P 37.65 30 UP S 20 GAIN = 18dB 37.60 GAIN = 24dB 10 GAIN = 30dB GAIN = 36dB 0 37.55 100k 1M 10M 100M
123
–40 –25 10 5 20 35 50 65 80 95 110 125
120
FREQUENCY (Hz) TEMPERATURE (°C)
13132- 13132- Figure 22. CMRR vs. Frequency at Various Gains Figure 24. Quiescent Supply Current vs. Temperature Rev. 0 | Page 10 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS DIGITAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE DEFAULT SPI SETTINGS INPUT IMPEDANCE POWER MODES PROGRAMMABLE GAIN RANGE OUTPUT SWING VARIATION WITH GAIN OFFSET VOLTAGE ADJUSTMENTS VIO Pin SINGLE-ENDED OR DIFFERENTIAL INPUT SHORT-CIRCUIT CURRENTS SPI INTERFACE CHANNEL TO CHANNEL PHASE MATCHING APPLICATIONS INFORMATION INCREASED GAIN USING TWO ADA8282 DEVICES IN SERIES MULTIPLEXING INPUTS USING MULTIPLE ADA8282 DEVICES BASIC CONNECTIONS FOR A TYPICAL APPLICATION REGISTER MAP REGISTER SUMMARY REGISTER DETAILS Register 0x00: Interface Configuration Register Register 0x01: Soft Reset Register Register 0x04: Chip ID Low Register Register 0x05: Chip ID High Register Register 0x06: Revision Register Register 0x10: LNA Offset 0 Register Register 0x11: LNA Offset 1 Register Register 0x12: LNA Offset 2 Register Register 0x13: LNA Offset 3 Register Register 0x14: PGA Bias Register Register 0x15: PGA Gain Register Register 0x17: Enable Channel Register Register 0x18: Enable Bias Generator Register Register 0x1D: GPIO Write Register Register 0x1E: GPIO Read Register OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
122
10k 100k 1M 10M 100M
124
FREQUENCY (Hz)
13132-
FREQUENCY (Hz)
13132- Figure 21. PSRR vs. Frequency at Various Gains Figure 23. Crosstalk vs. Frequency
100 37.85 90 37.80 80 70 mA) ( 37.75 60 B) NT d 50 37.70 RR ( CURRE CM 40 Y L P 37.65 30 UP S 20 GAIN = 18dB 37.60 GAIN = 24dB 10 GAIN = 30dB GAIN = 36dB 0 37.55 100k 1M 10M 100M
123
–40 –25 10 5 20 35 50 65 80 95 110 125
120
FREQUENCY (Hz) TEMPERATURE (°C)
13132- 13132- Figure 22. CMRR vs. Frequency at Various Gains Figure 24. Quiescent Supply Current vs. Temperature Rev. 0 | Page 10 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS DIGITAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE DEFAULT SPI SETTINGS INPUT IMPEDANCE POWER MODES PROGRAMMABLE GAIN RANGE OUTPUT SWING VARIATION WITH GAIN OFFSET VOLTAGE ADJUSTMENTS VIO Pin SINGLE-ENDED OR DIFFERENTIAL INPUT SHORT-CIRCUIT CURRENTS SPI INTERFACE CHANNEL TO CHANNEL PHASE MATCHING APPLICATIONS INFORMATION INCREASED GAIN USING TWO ADA8282 DEVICES IN SERIES MULTIPLEXING INPUTS USING MULTIPLE ADA8282 DEVICES BASIC CONNECTIONS FOR A TYPICAL APPLICATION REGISTER MAP REGISTER SUMMARY REGISTER DETAILS Register 0x00: Interface Configuration Register Register 0x01: Soft Reset Register Register 0x04: Chip ID Low Register Register 0x05: Chip ID High Register Register 0x06: Revision Register Register 0x10: LNA Offset 0 Register Register 0x11: LNA Offset 1 Register Register 0x12: LNA Offset 2 Register Register 0x13: LNA Offset 3 Register Register 0x14: PGA Bias Register Register 0x15: PGA Gain Register Register 0x17: Enable Channel Register Register 0x18: Enable Bias Generator Register Register 0x1D: GPIO Write Register Register 0x1E: GPIO Read Register OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS