Datasheet ADA8282 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Radar Receive Path AFE: 4-Channel LNA and PGA |
| 页数 / 页 | 21 / 8 — ADA8282. Data Sheet. GAIN = 36dB. GAIN = 30dB. ) IV. GAIN = 24dB. ANALOG … |
| 文件格式/大小 | PDF / 517 Kb |
| 文件语言 | 英语 |
ADA8282. Data Sheet. GAIN = 36dB. GAIN = 30dB. ) IV. GAIN = 24dB. ANALOG OUTPUT. GAIN = 18dB. T (. 250mV. B) d. N ( AI. LOG OU. A N. SDI. b'00. b'11. –12
该数据表的模型线
文件文字版本
ADA8282 Data Sheet 42 GAIN = 36dB 36 GAIN = 30dB 2V 30 ) IV GAIN = 24dB 24 /D ANALOG OUTPUT V GAIN = 18dB 1 18 T ( 250mV U B) d 12 TP N ( AI 6 G LOG OU 0 A N SDI A –6 b'00 b'11 –12 –18
105
–24 TIME (80ns/DIV)
13 1 13132-
100k 1M 10M 100M FREQUENCY (Hz)
13132- Figure 9. Gain Step Transient Response Figure 12. Frequency Response at All Gains (Bias Mode 0)
30 42 GAIN = 18dB GAIN = 36dB GAIN = 24dB 36 GAIN = 30dB 25 GAIN = 30dB GAIN = 36dB 30 GAIN = 24dB 24 20 GAIN = 18dB z) 18 √H V/ B) d 12 (n 15 N ( AI 6 ISE O G N 0 10 –6 5 –12 –18 0
1
–24
14
1k 10k 100k 1M 10M 100M
11
100k 1M 10M 100M
1
FREQUENCY (Hz)
13132-
FREQUENCY (Hz)
13132- Figure 10. Input Referred Noise vs. Frequency Figure 13. Frequency Response at All Gains (Bias Mode 2)
40 4 VIN × GAIN 35 3 VOUT 30 2 ) dB ( 25 1 E R E (V) D 20 50Ω U 0 IT FIGU E 15 MPL –1 OIS A N UNTERMINATED 10 –2 5 –3 0 –4
12 15
1k 10k 100k 1M 10M 100M
1
0 100 200 300 400 500 600 700 800
1
FREQUENCY (Hz)
13132-
TIME (ns)
13132- Figure 11. Noise Figure vs. Frequency Figure 14. Overdrive Recovery Rev. 0 | Page 8 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS DIGITAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE DEFAULT SPI SETTINGS INPUT IMPEDANCE POWER MODES PROGRAMMABLE GAIN RANGE OUTPUT SWING VARIATION WITH GAIN OFFSET VOLTAGE ADJUSTMENTS VIO Pin SINGLE-ENDED OR DIFFERENTIAL INPUT SHORT-CIRCUIT CURRENTS SPI INTERFACE CHANNEL TO CHANNEL PHASE MATCHING APPLICATIONS INFORMATION INCREASED GAIN USING TWO ADA8282 DEVICES IN SERIES MULTIPLEXING INPUTS USING MULTIPLE ADA8282 DEVICES BASIC CONNECTIONS FOR A TYPICAL APPLICATION REGISTER MAP REGISTER SUMMARY REGISTER DETAILS Register 0x00: Interface Configuration Register Register 0x01: Soft Reset Register Register 0x04: Chip ID Low Register Register 0x05: Chip ID High Register Register 0x06: Revision Register Register 0x10: LNA Offset 0 Register Register 0x11: LNA Offset 1 Register Register 0x12: LNA Offset 2 Register Register 0x13: LNA Offset 3 Register Register 0x14: PGA Bias Register Register 0x15: PGA Gain Register Register 0x17: Enable Channel Register Register 0x18: Enable Bias Generator Register Register 0x1D: GPIO Write Register Register 0x1E: GPIO Read Register OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS
105
–24 TIME (80ns/DIV)
13 1 13132-
100k 1M 10M 100M FREQUENCY (Hz)
13132- Figure 9. Gain Step Transient Response Figure 12. Frequency Response at All Gains (Bias Mode 0)
30 42 GAIN = 18dB GAIN = 36dB GAIN = 24dB 36 GAIN = 30dB 25 GAIN = 30dB GAIN = 36dB 30 GAIN = 24dB 24 20 GAIN = 18dB z) 18 √H V/ B) d 12 (n 15 N ( AI 6 ISE O G N 0 10 –6 5 –12 –18 0
1
–24
14
1k 10k 100k 1M 10M 100M
11
100k 1M 10M 100M
1
FREQUENCY (Hz)
13132-
FREQUENCY (Hz)
13132- Figure 10. Input Referred Noise vs. Frequency Figure 13. Frequency Response at All Gains (Bias Mode 2)
40 4 VIN × GAIN 35 3 VOUT 30 2 ) dB ( 25 1 E R E (V) D 20 50Ω U 0 IT FIGU E 15 MPL –1 OIS A N UNTERMINATED 10 –2 5 –3 0 –4
12 15
1k 10k 100k 1M 10M 100M
1
0 100 200 300 400 500 600 700 800
1
FREQUENCY (Hz)
13132-
TIME (ns)
13132- Figure 11. Noise Figure vs. Frequency Figure 14. Overdrive Recovery Rev. 0 | Page 8 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS DIGITAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE DEFAULT SPI SETTINGS INPUT IMPEDANCE POWER MODES PROGRAMMABLE GAIN RANGE OUTPUT SWING VARIATION WITH GAIN OFFSET VOLTAGE ADJUSTMENTS VIO Pin SINGLE-ENDED OR DIFFERENTIAL INPUT SHORT-CIRCUIT CURRENTS SPI INTERFACE CHANNEL TO CHANNEL PHASE MATCHING APPLICATIONS INFORMATION INCREASED GAIN USING TWO ADA8282 DEVICES IN SERIES MULTIPLEXING INPUTS USING MULTIPLE ADA8282 DEVICES BASIC CONNECTIONS FOR A TYPICAL APPLICATION REGISTER MAP REGISTER SUMMARY REGISTER DETAILS Register 0x00: Interface Configuration Register Register 0x01: Soft Reset Register Register 0x04: Chip ID Low Register Register 0x05: Chip ID High Register Register 0x06: Revision Register Register 0x10: LNA Offset 0 Register Register 0x11: LNA Offset 1 Register Register 0x12: LNA Offset 2 Register Register 0x13: LNA Offset 3 Register Register 0x14: PGA Bias Register Register 0x15: PGA Gain Register Register 0x17: Enable Channel Register Register 0x18: Enable Bias Generator Register Register 0x1D: GPIO Write Register Register 0x1E: GPIO Read Register OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS