Datasheet ST7LITEUSx (STMicroelectronics) - 36
| 制造商 | STMicroelectronics |
| 描述 | 8-bit MCU with single voltage Flash memory, ADC, timers. ST7ULTRALITE (ST7LITEUS2, ST7LITEUS5) |
| 页数 / 页 | 108 / 36 — ST7LITEUSx. POWER SAVING MODES. 8.4.2 HALT MODE. Figure 24. HALT Mode … |
| 文件格式/大小 | PDF / 889 Kb |
| 文件语言 | 英语 |
ST7LITEUSx. POWER SAVING MODES. 8.4.2 HALT MODE. Figure 24. HALT Mode Flow-chart. HALT. Figure 23. HALT Timing Overview. Notes:
该数据表的模型线
- ST7FLITEUS2B3 ST7FLITEUS2B6 ST7FLITEUS2M3 ST7FLITEUS2M3TR ST7FLITEUS2M6 ST7FLITEUS2M6TR ST7FLITEUS2U3TR ST7FLITEUS2U6TR ST7FLITEUS5B3 ST7FLITEUS5B6 ST7FLITEUS5M3 ST7FLITEUS5M3TR ST7FLITEUS5M6 ST7FLITEUS5M6TR ST7FLITEUS5U3 ST7FLITEUS5U3TR ST7FLITEUS5U6 ST7FLITEUS5U6TR ST7FLITEUSICD ST7PLITEUS2B3 ST7PLITEUS2B6 ST7PLITEUS2M3 ST7PLITEUS2M3TR ST7PLITEUS2M6 ST7PLITEUS2M6TR ST7PLITEUS2U3TR ST7PLITEUS2U6TR ST7PLITEUS5B3 ST7PLITEUS5B6 ST7PLITEUS5M3 ST7PLITEUS5M3TR ST7PLITEUS5M6 ST7PLITEUS5M6TR ST7PLITEUS5U3 ST7PLITEUS5U3TR ST7PLITEUS5U6 ST7PLITEUS5U6TR
文件文字版本
ST7LITEUSx POWER SAVING MODES
(Cont’d)
8.4.2 HALT MODE
The HALT mode is the lowest power consumption
Figure 24. HALT Mode Flow-chart
mode of the MCU. It is entered by executing the ‘HALT’ instruction when active halt mode is disa-
HALT
INSTRUCTION bled. (Active Halt disabled) The MCU can exit HALT mode on reception of ei- ENABLE WATCHDOG ther a specific interrupt (see Table 7, “Interrupt Mapping,” on page 26) or a RESET. When exiting DISABLE HALT mode by means of a RESET or an interrupt, WDGHALT 1) 0 the main oscillator is immediately turned on and 1 the 64 CPU cycle delay is used to stabilize it. After the start up delay, the CPU resumes operation by WATCHDOG OSCILLATOR servicing the interrupt or by fetching the reset vec- OFF RESET PERIPHERALS 2) tor which woke it up (see Figure 24). OFF CPU OFF When entering HALT mode, the I bit in the CC reg- I BIT 0 ister is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immedi- ately. N RESET In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, in- Y N cluding the operation of the on-chip peripherals. INTERRUPT 3) All peripherals are not clocked except the ones which get their clock supply from another clock Y OSCILLATOR ON generator (such as an external or auxiliary oscilla- PERIPHERALS OFF tor). CPU ON I BIT X 4) The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT” op- tion bit of the option byte. The HALT instruction 64 CPU CLOCK CYCLE when executed while the Watchdog system is en- DELAY 5) abled, can generate a Watchdog RESET (see sec- tion 14.1 on page 95 for more details). OSCILLATOR ON PERIPHERALS ON
Figure 23. HALT Timing Overview
CPU ON I BITS X 4) 64 CPU CYCLE RUN HALT RUN DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT RESET
Notes:
OR HALT INTERRUPT
1.
WDGHALT is an option bit. See option byte sec- INSTRUCTION FETCH tion for more details. [Active Halt disabled] VECTOR
2.
Peripheral clocked with an external clock source
Note:
can still be active.
1.
A reset pulse of at least 42µs must be applied
3.
Only some specific interrupts can exit the MCU when exiting from HALT mode. from HALT mode (such as external interrupt). Re- fer to Table 7, “Interrupt Mapping,” on page 26 for more details.
4.
Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
5.
The CPU clock must be switched to 1MHz (RC/8) or AWU RC before entering HALT mode. 36/108 1
(Cont’d)
8.4.2 HALT MODE
The HALT mode is the lowest power consumption
Figure 24. HALT Mode Flow-chart
mode of the MCU. It is entered by executing the ‘HALT’ instruction when active halt mode is disa-
HALT
INSTRUCTION bled. (Active Halt disabled) The MCU can exit HALT mode on reception of ei- ENABLE WATCHDOG ther a specific interrupt (see Table 7, “Interrupt Mapping,” on page 26) or a RESET. When exiting DISABLE HALT mode by means of a RESET or an interrupt, WDGHALT 1) 0 the main oscillator is immediately turned on and 1 the 64 CPU cycle delay is used to stabilize it. After the start up delay, the CPU resumes operation by WATCHDOG OSCILLATOR servicing the interrupt or by fetching the reset vec- OFF RESET PERIPHERALS 2) tor which woke it up (see Figure 24). OFF CPU OFF When entering HALT mode, the I bit in the CC reg- I BIT 0 ister is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immedi- ately. N RESET In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, in- Y N cluding the operation of the on-chip peripherals. INTERRUPT 3) All peripherals are not clocked except the ones which get their clock supply from another clock Y OSCILLATOR ON generator (such as an external or auxiliary oscilla- PERIPHERALS OFF tor). CPU ON I BIT X 4) The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT” op- tion bit of the option byte. The HALT instruction 64 CPU CLOCK CYCLE when executed while the Watchdog system is en- DELAY 5) abled, can generate a Watchdog RESET (see sec- tion 14.1 on page 95 for more details). OSCILLATOR ON PERIPHERALS ON
Figure 23. HALT Timing Overview
CPU ON I BITS X 4) 64 CPU CYCLE RUN HALT RUN DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT RESET
Notes:
OR HALT INTERRUPT
1.
WDGHALT is an option bit. See option byte sec- INSTRUCTION FETCH tion for more details. [Active Halt disabled] VECTOR
2.
Peripheral clocked with an external clock source
Note:
can still be active.
1.
A reset pulse of at least 42µs must be applied
3.
Only some specific interrupts can exit the MCU when exiting from HALT mode. from HALT mode (such as external interrupt). Re- fer to Table 7, “Interrupt Mapping,” on page 26 for more details.
4.
Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
5.
The CPU clock must be switched to 1MHz (RC/8) or AWU RC before entering HALT mode. 36/108 1