Datasheet AD73322L (Analog Devices) - 5

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AD73322L A and Y Versions Parameter Min Typ Max Unit Test Conditions/Comments
Group Delay3, 4 25 µs Input Resistance at PGA1, 3, 5 20 kΩ Input amplifiers bypassed DIGITAL GAIN TAP Gain at Maximum Setting 1 Gain at Minimum Setting −1 Gain Resolution 16 Bits Tested to 5 MSB of settings Delay 25 µs Includes DAC delay Settling Time 100 µs Tap gain change from −FS to +FS; includes DAC settling time DAC SPECIFICATIONS DAC unloaded Maximum Voltage Output Swing1 Single-Ended 1.578 V p-p PGA = 6 dB −2.85 dBm Max output = (1.578/1.2) × VREFCAP Differential 3.156 V p-p PGA = 6 dB 3.17 dBm Max output = 2 × (1.578/1.2) × VREFCAP Nominal Voltage Output Swing (0 dBm0) Single-Ended 1.0954 V p-p PGA = 6 dB −6.02 dBm Differential 2.1909 V p-p PGA = 6 dB 0 dBm Output Bias Voltage 1.2 V REFOUT unloaded Absolute Gain −1.75 −0.6 +0.75 dB 1.0 kHz, 0 dBm0; unloaded Gain Tracking Error ±0.1 dB 1.0 kHz, +3 dBm0 to −50 dBm0 Signal-to-Noise and Distortion at 0 dBm0 Refer to Figure 10 PGA = 0 dB 72 78.5 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz Total Harmonic Distortion at 0 dBm0 PGA = 0 dB −89 −75 dB 300 Hz to 3400 Hz; fSAMP = 8 kHz Intermodulation Distortion −77 dB PGA = 0 dB Idle Channel Noise Crosstalk −81 dBm0 PGA = 0 dB DAC-to-ADC −73 dB ADC input signal level: AGND; DAC output signal level: 1.0 kHz, 0 dBm0 Input amplifiers bypassed −74 dB Input amplifiers included in input channel DAC-to-DAC −102 dB DAC1 output signal level: AGND; DAC2 Output signal level: 1.0 kHz, 0 dBm0 Power Supply Rejection −65 dB Input signal level at AVDD and DVDD pins: 1.0 kHz, 100 mV p-p sine wave Group Delay3, 4 25 µs Interpolator bypassed 50 µs Output DC Offset1, 6 −50 +5 +60 mV Minimum Load Resistance, R 1, 7 L Single-Ended3 150 Ω Differential 150 Ω Maximum Load Capacitance, C 1, 7 L Single-Ended 500 pF Differential 100 pF FREQUENCY RESPONSE (ADC and DAC)8 Typical Output Frequency (Normalized to FS) 0 0 dB 0.03125 −0.1 dB Rev. A | Page 5 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS CURRENT SUMMARY SIGNAL RANGES TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY ABBREVIATIONS TYPICAL PERFORMANCE CHARACTERISTICS AND FUNCTIONAL BLOCK DIA FUNCTIONAL DESCRIPTIONS ENCODER CHANNELS PROGRAMMABLE GAIN AMPLIFIER ADC ANALOG SIGMA-DELTA MODULATOR DECIMATION FILTER ADC CODING DECODER CHANNEL DAC CODING INTERPOLATION FILTER ANALOG SMOOTHING FILTER AND PGA DIFFERENTIAL OUTPUT AMPLIFIERS VOLTAGE REFERENCE ANALOG AND DIGITAL GAIN TAPS DIGITAL GAIN TAP SERIAL PORT (SPORT) SPORT OVERVIEW SPORT REGISTER MAPS MASTER CLOCK DIVIDER SERIAL CLOCK RATE DIVIDER SAMPLE RATE DIVIDER DAC ADVANCE REGISTER CONTROL REGISTER A CONTROL REGISTER B CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E CONTROL REGISTER F CONTROL REGISTER G CONTROL REGISTER H OPERATION RESETTING THE AD73322L POWER MANAGEMENT OPERATING MODES PROGRAM (CONTROL) MODE DATA MODE MIXED PROGRAM/DATA MODE DIGITAL LOOP-BACK MODE SPORT LOOP-BACK MODE ANALOG LOOP-BACK MODE INTERFACING CASCADE OPERATION PERFORMANCE ENCODER SECTION ENCODER GROUP DELAY DECODER SECTION ON-CHIP FILTERING DECODER GROUP DELAY DESIGN CONSIDERATIONS ANALOG INPUTS INTERFACING TO AN ELECTRET MICROPHONE ANALOG OUTPUT DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT DIGITAL INTERFACING CASCADE OPERATION GROUNDING AND LAYOUT DSP PROGRAMMING CONSIDERATIONS DSP SPORT CONFIGURATION DSP SPORT INTERRUPTS DSP SOFTWARE CONSIDERATIONS WHEN INTERFACING TO THE AD73322L OPERATING MODE MIXED-MODE OPERATION INTERRUPTS INITIALIZATION RUNNING THE AD73322L WITH ADCS OR DACS IN POWER-DOWN DAC TIMING CONTROL EXAMPLE CONFIGURING AN AD73322L TO OPERATE IN DATA MODE CONFIGURING AN AD73322L TO OPERATE IN MIXED MODE OUTLINE DIMENSIONS ORDERING GUIDE