Datasheet AD73322L (Analog Devices) - 6

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AD73322L A and Y Versions Parameter Min Typ Max Unit Test Conditions/Comments
0.0625 −0.25 dB 0.125 −0.6 dB 0.1875 −1.4 dB 0.25 −2.8 dB 0.3125 − 4.5 dB 0.375 −7.0 dB 0.4375 −9.5 dB > 0.5 <−12.5 dB LOGIC INPUTS VINH, Input High Voltage DVDD − 0.8 DVDD V VINL, Input Low Voltage 0 0.8 V IIH, Input Current −10 +10 µA CIN, Input Capacitance 10 pF LOGIC OUTPUT VOH, Output High Voltage DVDD − 0.4 DVDD V |IOUT| ≤100 µA VOL, Output Low Voltage 0 0.4 V |IOUT| ≤100 µA Three-State Leakage Current −10 +10 µA POWER SUPPLIES AVDD1, AVDD2 2.7 3.3 V 2.7 3.3 V DVDD I 9 DD See Table 2 1 Test conditions: input PGA set for 0 dB gain, output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted). 2 At input to sigma-delta modulator of ADC. 3 Guaranteed by design. 4 Overall group delay is affected by the sample rate and the external digital filtering. 5 The ADC’s input impedance is inversely proportional to DMCLK and is approximated by (3/3 × 1011)/DMCLK. 6 Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2. 7 At VOUT output. 8 Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of −10 dBm0), with 38 dB preamplifier bypassed and input gain of 0 dB. 9 Test conditions: no load on digital inputs, analog inputs ac-coupled to ground, no load on analog outputs.
CURRENT SUMMARY
AVDD = DVDD = 3.3 V. These values are in mA and are typical values unless otherwise noted.
Table 2. Analog Digital Total Total Conditions Current Current Current (Typ) Current (Max) SE MCLK ON Comments
ADCs on only 3.4 6.3 9.7 12 1 YES REFOUT disabled DACs on only 8.8 6.5 15.3 20 1 YES REFOUT disabled ADCs and DACs on 11.6 7.0 18.6 23 1 YES REFOUT disabled ADCs and DACs and 13.8 7.0 20.8 26 1 YES REFOUT disabled Input amps on ADCs and DACs and 13.2 7.0 20.2 26 1 YES REFOUT disabled AGT on All sections on 17.2 7.0 24.2 31 1 YES REFCAP on only 0.65 0 0.67 1.25 0 NO REFOUT disabled REFCAP and REFOUT 2.56 0 2.57 4.5 0 NO On only All sections off 0 1.25 1.25 1.8 0 YES MCLK active levels equal to 0 V and DVDD All sections off 0 µA 12.5 µA 12.7 µA 40 µA 0 NO Digital inputs static and Equal to 0 V or DVDD Rev. A | Page 6 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS CURRENT SUMMARY SIGNAL RANGES TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY ABBREVIATIONS TYPICAL PERFORMANCE CHARACTERISTICS AND FUNCTIONAL BLOCK DIA FUNCTIONAL DESCRIPTIONS ENCODER CHANNELS PROGRAMMABLE GAIN AMPLIFIER ADC ANALOG SIGMA-DELTA MODULATOR DECIMATION FILTER ADC CODING DECODER CHANNEL DAC CODING INTERPOLATION FILTER ANALOG SMOOTHING FILTER AND PGA DIFFERENTIAL OUTPUT AMPLIFIERS VOLTAGE REFERENCE ANALOG AND DIGITAL GAIN TAPS DIGITAL GAIN TAP SERIAL PORT (SPORT) SPORT OVERVIEW SPORT REGISTER MAPS MASTER CLOCK DIVIDER SERIAL CLOCK RATE DIVIDER SAMPLE RATE DIVIDER DAC ADVANCE REGISTER CONTROL REGISTER A CONTROL REGISTER B CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E CONTROL REGISTER F CONTROL REGISTER G CONTROL REGISTER H OPERATION RESETTING THE AD73322L POWER MANAGEMENT OPERATING MODES PROGRAM (CONTROL) MODE DATA MODE MIXED PROGRAM/DATA MODE DIGITAL LOOP-BACK MODE SPORT LOOP-BACK MODE ANALOG LOOP-BACK MODE INTERFACING CASCADE OPERATION PERFORMANCE ENCODER SECTION ENCODER GROUP DELAY DECODER SECTION ON-CHIP FILTERING DECODER GROUP DELAY DESIGN CONSIDERATIONS ANALOG INPUTS INTERFACING TO AN ELECTRET MICROPHONE ANALOG OUTPUT DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT DIGITAL INTERFACING CASCADE OPERATION GROUNDING AND LAYOUT DSP PROGRAMMING CONSIDERATIONS DSP SPORT CONFIGURATION DSP SPORT INTERRUPTS DSP SOFTWARE CONSIDERATIONS WHEN INTERFACING TO THE AD73322L OPERATING MODE MIXED-MODE OPERATION INTERRUPTS INITIALIZATION RUNNING THE AD73322L WITH ADCS OR DACS IN POWER-DOWN DAC TIMING CONTROL EXAMPLE CONFIGURING AN AD73322L TO OPERATE IN DATA MODE CONFIGURING AN AD73322L TO OPERATE IN MIXED MODE OUTLINE DIMENSIONS ORDERING GUIDE