Datasheet AD5592R (Analog Devices) - 4

link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7
AD5592R Data Sheet SPECIFICATIONS
VDD = 2.7 V to 5.5 V, VREF = 2.5 V (external), RL = 2 kΩ to GND, CL = 200 pF to GND, TA = TMIN to TMAX, temperature range = −40°C to +105°C, unless otherwise noted.
Table 2. Parameter Min Typ Max Unit1 Test Conditions/Comments
ADC PERFORMANCE fIN = 10 kHz sine wave Resolution 12 Bits Input Range 0 VREF V When using the internal ADC buffer, there is a dead band of 0 V to 5 mV 0 2 × VREF V Integral Nonlinearity (INL) −2 +2 LSB Differential Nonlinearity (DNL) −1 +1 LSB Offset Error ±5 mV Gain Error 0.3 % FSR Throughput Rate2 400 kSPS Track Time (tTRACK)2 500 ns Conversion Time (tCONV)2 2 µs Signal-to-Noise Ratio (SNR) 69 dB VDD = 2.7 V, input range = 0 V to VREF 67 dB VDD = 5.5 V, input range = 0 V to VREF 61 dB VDD = 5.5 V, input range = 0 V to 2 × VREF Signal-to-Noise-and-Distortion (SINAD) Ratio 69 dB VDD = 2.7 V, input range = 0 V to VREF 67 dB VDD = 3.3 V, input range = 0 V to VREF 60 dB VDD = 5.5 V, input range = 0 V to 2 × VREF Total Harmonic Distortion (THD) −91 dB VDD = 2.7 V, input range = 0 V to VREF −89 dB VDD = 3.3 V, input range = 0 V to VREF −72 dB VDD = 5.5 V, input range = 0 V to 2 × VREF Peak Harmonic or Spurious Noise (SFDR) 91 dB VDD = 2.7 V, input range = 0 V to VREF 91 dB VDD = 3.3 V, input range = 0 V to VREF 72 dB VDD = 5.5 V, input range = 0 V to 2 × VREF Aperture Delay2 15 ns VDD = 3 V 12 ns VDD = 5 V Aperture Jitter2 50 ps Channel-to-Channel Isolation −95 dB fIN = 5 kHz Input Capacitance 45 pF Full Power Bandwidth 8.2 MHz At 3 dB 1.6 MHz At 0.1 dB DAC PERFORMANCE3 Resolution 12 Bits Output Range 0 VREF V 0 2 × VREF V Integral Nonlinearity (INL) −1 +1 LSB Differential Nonlinearity (DNL) −1 +1 LSB Offset Error −3 +3 mV Offset Error Drift2 8 µV/°C Gain Error ±0.2 % FSR Output range = 0 V to VREF ±0.1 % FSR Output range = 0 V to 2 × VREF Zero Code Error 0.65 2 mV Total Unadjusted Error ±0.03 ±0.25 % FSR Output range = 0 V to VREF ±0.015 ±0.1 Output range = 0 V to 2 × VREF Capacitive Load Stability2 2 nF RLOAD = ∞ 10 nF RLOAD = 1 kΩ Resistive Load 1 kΩ Short-Circuit Current 25 mA Rev. E | Page 4 of 43 Document Outline Features Applications General Description Functional Block Diagram Revision History Functional Block Diagram (AD5592R-1) Specifications Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology ADC Terminology DAC Terminology Theory of Operation DAC Section Resistor String Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference RESETB Function Temperature Indicator Serial Interface Power-Up Time Write Mode Read Mode Configuring the AD5592R/AD5592R-1 General-Purpose Control Register DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation Changing an ADC Sequence GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Resistor Pins Power-Down Mode Reset Function Readback and LDAC Mode Register Applications Information Microprocessor Interfacing AD5592R/AD5592R-1 to SPI Interface AD5592R/AD5592R-1 to SPORT Interface Layout Guidelines Outline Dimensions Ordering Guide