Datasheet AD5592R (Analog Devices) - 5

link to page 7 link to page 7 link to page 7 link to page 7 link to page 7
Data Sheet AD5592R Parameter Min Typ Max Unit1 Test Conditions/Comments
DC Crosstalk2 −4 +4 µV Due to single channel, ful -scale output change DC Output Impedance 0.2 Ω DC Power Supply Rejection Ratio (PSRR)2 0.15 mV/V DAC code = midscale, VDD = 3 V ± 10% or 5 V ± 10% Load Impedance at Rails4 25 Ω Load Regulation 200 µV/mA VDD = 5 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤ +10 mA 200 µV/mA VDD = 3 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤ +10 mA Power-Up Time 7 µs Coming out of power-down mode, VDD = 5 V AC SPECIFICATIONS Slew Rate 1.25 V/µs Measured from 10% to 90% of full scale Settling Time 6 µs ¼ scale to ¾ scale settling to 1 LSB DAC Glitch Impulse 2 nV-sec DAC to DAC Crosstalk 1 nV-sec Digital Crosstalk 0.1 nV-sec Analog Crosstalk 1 nV-sec Digital Feedthrough 0.1 nV-sec Multiplying Bandwidth 240 kHz DAC code = ful scale, output range = 0 V to VREF Output Voltage Noise Spectral Density 200 nV/√Hz DAC code = midscale, output range = 0 V to 2 × VREF, measured at 10 kHz Signal-to-Noise Ratio (SNR) 81 dB Peak Harmonic or Spurious Noise (SFDR) 77 dB Signal-to-Noise-and-Distortion (SINAD) Ratio 74 dB Total Harmonic Distortion (THD) −76 dB REFERENCE INPUT VREF Input Voltage 1 VDD V DC Leakage Current −1 +1 µA No I/Ox pins configured as DACs Reference Input Impedance 12 kΩ DAC output range = 0 V to 2 × VREF 24 kΩ DAC output range = 0 V to VREF REFERENCE OUTPUT VREF Output Voltage 2.495 2.5 2.505 V At ambient VREF Temperature Coefficient 20 ppm/°C Capacitive Load Stability 5 μF RL = 2 kΩ Output Impedance2 0.15 Ω VDD = 2.7 V 0.7 Ω VDD = 5 V Output Voltage Noise 10 µV p-p 0.1 Hz to 10 Hz Output Voltage Noise Density 240 nV/√Hz At ambient, f = 10 kHz, CL = 10 nF Line Regulation 20 µV/V At ambient, sweeping VDD from 2.7 V to 5.5 V 10 µV/V At ambient, sweeping VDD from 2.7 V to 3.3 V Load Regulation Sourcing 210 µV/mA At ambient, −5 mA ≤ load current ≤ +5 mA Sinking 120 µV/mA At ambient, −5 mA ≤ load current ≤ +5 mA Output Current Load Capability ±5 mA VDD ≥ 3 V GPIO OUTPUT ISOURCE, ISINK 1.6 mA Output Voltage High (VOH) VDD − 0.2 V ISOURCE = 1 mA Low (VOL) 0.4 V ISOURCE = 1 mA Rev. E | Page 5 of 43 Document Outline Features Applications General Description Functional Block Diagram Revision History Functional Block Diagram (AD5592R-1) Specifications Timing Characteristics Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology ADC Terminology DAC Terminology Theory of Operation DAC Section Resistor String Output Buffer ADC Section Calculating ADC Input Current GPIO Section Internal Reference RESETB Function Temperature Indicator Serial Interface Power-Up Time Write Mode Read Mode Configuring the AD5592R/AD5592R-1 General-Purpose Control Register DAC Write Operation LDAC Mode Operation DAC Readback ADC Operation Changing an ADC Sequence GPIO Operation Setting Pins as Outputs Setting Pins as Inputs Three-State Pins 85 kΩ Pull-Down Resistor Pins Power-Down Mode Reset Function Readback and LDAC Mode Register Applications Information Microprocessor Interfacing AD5592R/AD5592R-1 to SPI Interface AD5592R/AD5592R-1 to SPORT Interface Layout Guidelines Outline Dimensions Ordering Guide