Datasheet AD9364 (Analog Devices)

RF Agile Transceiver Data Sheet AD9364 FEATURES FUNCTIONAL BLOCK DIAGRAM RF 1 × 1 transceiver with integrated 12-bit DACs and ADCs Band: 70 MHz to 6.0 GHz RXB_P, AD9364 RXB_N Supports time division duplex (TDD) and frequency division RXA_P, RXA_N ADC E duplex (FDD) operation AC RXC_P, P0_[D11:D0]/ Tunable channel bandwidth (BW): <200 kHz to 56 MHz RXC_N Rx LO RF TX_[D5:D0] E 3-band receiver: 3 differential or 6 single-ended inputs NT P1_[D11:D0]/ TX_MON I Tx LO A RX_[D5:D0] Superior receiver sensitivity with a noise figure of <2.5 dB T TXA_P, DAC DA TXA_N Rx gain control TXB_P, Real-time monitor and control signals for manual gain TXB_N RADIO Independent automatic gain control GPO SWITCHING ADC DAC DAC 2-band differential output transmitter SPI CTRL PLLs CLK_OUT Highly linear broadband transmitter CTRL Tx EVM: ≤−40 dB AUXADC AUXDACx XTALN Tx noise: ≤−157 dBm/Hz noise floor NOTES
-001
1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0], Tx monitor: ≥66 dB dynamic range with 1 dB accuracy AND RADIO SWITCHING CONTAIN MULTIPLE PINS.
1846 1
Integrated fractional-N synthesizers
Figure 1.
2.4 Hz maximum local oscillator (LO) step size Multichip synchronization CMOS/LVDS digital interface APPLICATIONS Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems GENERAL DESCRIPTION
The AD9364 is a high performance, highly integrated radio fre- and 128-tap FIR filters to produce a 12-bit output signal at the quency (RF) Agile Transceiver™ designed for use in 3G and 4G base appropriate sample rate. station applications. Its programmability and wideband capability The transmitter uses a direct conversion architecture that achieves make it ideal for a broad range of transceiver applications. high modulation accuracy with ultralow noise. This transmitter The device combines an RF front end with a flexible mixed-signal design produces a Tx EVM of ≤−40 dB, allowing significant system baseband section and integrated frequency synthesizers, simpli- margin for the external power amplifier (PA) selection. The on- fying design-in by providing a configurable digital interface to a board transmit (Tx) power monitor can be used as a power processor. The AD9364 operates in the 70 MHz to 6.0 GHz range, detector, enabling highly accurate Tx power measurements. covering most licensed and unlicensed bands. Channel bandwidths The fully integrated phase-locked loops (PLLs) provide low from less than 200 kHz to 56 MHz are supported. power fractional-N frequency synthesis for all Rx and Tx channels. The direct conversion receiver has state-of-the-art noise figure All VCO and loop filter components are integrated. and linearity. The receive (Rx) subsystem includes independent The core of the AD9364 can be powered directly from a 1.3 V automatic gain control (AGC), dc offset correction, quadrature regulator. The IC is controlled via a standard 4-wire serial port and correction, and digital filtering, thereby eliminating the need for four real-time input control pins. Comprehensive power-down these functions in the digital baseband. The AD9364 also has modes are included to minimize power consumption during flexible manual gain modes that can be externally controlled. normal use. The AD9364 is packaged in a 10 mm × 10 mm, Two high dynamic range ADCs digitize the received I and Q 144-ball chip scale package ball grid array (CSP_BGA). signals and pass them through configurable decimation filters
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Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide