Datasheet AD9364 (Analog Devices) - 3

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Data Sheet AD9364 SPECIFICATIONS
Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and al other VDDx pins = 1.3 V, TA = 25°C, unless otherwise noted.
Table 1. Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
RECEIVER, GENERAL Center Frequency 70 6000 MHz Gain Minimum 0 dB Maximum 74.5 dB At 800 MHz 73.0 dB At 2300 MHz, RXA 72.0 dB At 2300 MHz, RXB, RXC 65.5 dB At 5500 MHz, RXA Gain Step 1 dB Received Signal Strength RSSI Indicator Range 100 dB Accuracy ±2 dB RECEIVER, 800 MHz Noise Figure NF 2 dB Maximum Rx gain Third-Order Input Intermod- IIP3 −18 dBm Maximum Rx gain ulation Intercept Point Second-Order Input Intermod- IIP2 40 dBm Maximum Rx gain ulation Intercept Point Local Oscil ator (LO) Leakage −122 dBm At Rx front-end input Quadrature Gain Error 0.2 % Phase Error 0.2 Degrees Modulation Accuracy (EVM) −42 dB 19.2 MHz reference clock Input S11 −10 dB RECEIVER, 2.4 GHz Noise Figure NF 3 dB Maximum Rx gain Third-Order Input Intermod- IIP3 −14 dBm Maximum Rx gain ulation Intercept Point Second-Order Input Intermod- IIP2 45 dBm Maximum Rx gain ulation Intercept Point Local Oscil ator (LO) Leakage −110 dBm At Rx front-end input Quadrature Gain Error 0.2 % Phase Error 0.2 Degrees Modulation Accuracy (EVM) −42 dB 40 MHz reference clock Input S11 −10 dB RECEIVER, 5.5 GHz Noise Figure NF 3.8 dB Maximum Rx gain Third-Order Input Intermod- IIP3 −17 dBm Maximum Rx gain ulation Intercept Point Second-Order Input Intermod- IIP2 42 dBm Maximum Rx gain ulation Intercept Point Local Oscil ator (LO) Leakage −95 dBm At Rx front-end input Quadrature Gain Error 0.2 % Phase Error 0.2 Degrees Modulation Accuracy (EVM) −37 dB 40 MHz reference clock (doubled internally for RF synthesizer) Input S11 −10 dB TRANSMITTER—GENERAL Center Frequency 70 6000 MHz Power Control Range 90 dB Power Control Resolution 0.25 dB Rev. C | Page 3 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide