Datasheet AD9364 (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | RF Agile Transceiver |
| 页数 / 页 | 32 / 2 — AD9364. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 7/14—Rev. B to … |
| 修订版 | C |
| 文件格式/大小 | PDF / 592 Kb |
| 文件语言 | 英语 |
AD9364. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 7/14—Rev. B to Rev. C. 2/14—Revision B: Initial Version
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AD9364 Data Sheet TABLE OF CONTENTS
Features .. 1 5.5 GHz Frequency Band .. 24 Applications ... 1 Theory of Operation .. 28 Functional Block Diagram .. 1 General... 28 General Description ... 1 Receiver.. 28 Revision History ... 2 Transmitter .. 28 Specifications ... 3 Clock Input Options .. 28 Current Consumption—VDD_Interface .. 7 Synthesizers ... 29 Current Consumption—VDDD1P3_DIG and VDDAx Digital Data Interface... 29 (Combination of All 1.3 V Supplies) ... 8 Enable State Machine ... 29 Absolute Maximum Ratings ... 10 SPI Interface .. 30 Reflow Profile .. 10 Control Pins .. 30 Thermal Resistance .. 10 GPO Pins (GPO_3 to GPO_0) ... 30 ESD Caution .. 10 Auxiliary Converters .. 30 Pin Configuration and Function Descriptions ... 11 Powering the AD9364 .. 30 Typical Performance Characteristics ... 15 Packaging and Ordering Information ... 31 800 MHz Frequency Band ... 15 Outline Dimensions ... 31 2.4 GHz Frequency Band .. 20 Ordering Guide .. 31
REVISION HISTORY 7/14—Rev. B to Rev. C
Changed CMOS VDD_INTERFACE from 1.2 V (min)/2.5 V (max) to 1.14 V (min)/2.625 V (max); and Changed LVDS VDD_INTERFACE from 1.8 V (min)/2.5 V (max) to 1.71 V (min)/2.625 V (max); Table 1... 7 Added Powering the AD9364 Section ... 30
2/14—Revision B: Initial Version
Rev. C | Page 2 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide
AD9364 Data Sheet TABLE OF CONTENTS
Features .. 1 5.5 GHz Frequency Band .. 24 Applications ... 1 Theory of Operation .. 28 Functional Block Diagram .. 1 General... 28 General Description ... 1 Receiver.. 28 Revision History ... 2 Transmitter .. 28 Specifications ... 3 Clock Input Options .. 28 Current Consumption—VDD_Interface .. 7 Synthesizers ... 29 Current Consumption—VDDD1P3_DIG and VDDAx Digital Data Interface... 29 (Combination of All 1.3 V Supplies) ... 8 Enable State Machine ... 29 Absolute Maximum Ratings ... 10 SPI Interface .. 30 Reflow Profile .. 10 Control Pins .. 30 Thermal Resistance .. 10 GPO Pins (GPO_3 to GPO_0) ... 30 ESD Caution .. 10 Auxiliary Converters .. 30 Pin Configuration and Function Descriptions ... 11 Powering the AD9364 .. 30 Typical Performance Characteristics ... 15 Packaging and Ordering Information ... 31 800 MHz Frequency Band ... 15 Outline Dimensions ... 31 2.4 GHz Frequency Band .. 20 Ordering Guide .. 31
REVISION HISTORY 7/14—Rev. B to Rev. C
Changed CMOS VDD_INTERFACE from 1.2 V (min)/2.5 V (max) to 1.14 V (min)/2.625 V (max); and Changed LVDS VDD_INTERFACE from 1.8 V (min)/2.5 V (max) to 1.71 V (min)/2.625 V (max); Table 1... 7 Added Powering the AD9364 Section ... 30
2/14—Revision B: Initial Version
Rev. C | Page 2 of 32 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Current Consumption—VDD_Interface Current Consumption—VDDD1P3_DIG and VDDAx (Combination of All 1.3 V Supplies) Absolute Maximum Ratings Reflow Profile Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 800 MHz Frequency Band 2.4 GHz Frequency Band 5.5 GHz Frequency Band Theory of Operation General Receiver Transmitter Clock Input Options Synthesizers RF PLLs BB PLL Digital Data Interface DATA_CLK Signal FB_CLK Signal RX_FRAME Signal Enable State Machine SPI Control Mode Pin Control Mode SPI Interface Control Pins Control Outputs (CTRL_OUT7 to CTRL_OUT0) Control Inputs (CTRL_IN3 to CTRL_IN0) GPO Pins (GPO_3 to GPO_0) Auxiliary Converters AUXADC AUXDAC1 and AUXDAC2 Powering the AD9364 Packaging and Ordering Information Outline Dimensions Ordering Guide