Datasheet ADN8835 (Analog Devices) - 5

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Data Sheet ADN8835 Parameter Symbol Test Conditions/Comments Min Typ Max Unit
EN/SY Input Voltage Low VEN/SY_ILOW 0.8 V High VEN/SY_IHIGH 2.1 V External Synchronization Frequency fSYNC 1.85 3.25 MHz Synchronization Pulse Duty Cycle DSYNC 10 90 % EN/SY Rising to PWM Rising Delay tSYNC_PWM 50 ns EN/SY to PWM Lock Time tSY_LOCK Number of sync cycles 11 Cycles EN/SY Input Current IEN/SY 0.3 0.5 µA Pul -Down Current 0.3 0.5 µA ERROR/COMPENSATION AMPLIFIERS Input Offset Voltage VOS1 VCM1 = 1.5 V, VOS1 = VIN1P − VIN1N 10 100 µV VOS2 VCM2 = 1.5 V, VOS2 = VIN2P − VIN2N 10 100 µV Input Voltage Range VCM1, VCM2 0 VVDD V Common-Mode Rejection Ratio (CMRR) CMRR1, CMRR2 VCM1, VCM2 = 0.2 V to VVDD − 0.2 V 120 dB Output Voltage High VOH1, VOH2 VVDD − V 0.04 Low VOL1, VOL2 10 mV Power Supply Rejection Ratio (PSRR) PSRR1, PSRR2 120 dB Output Current IOUT1, IOUT2 Sourcing and sinking 5 mA Gain Bandwidth Product1 GBW1, GBW2 VOUT1, VOUT2 = 0.5 V to VVDD − 1 V 2 MHz TEC CURRENT LIMIT ILIM Input Voltage Range Cooling VILIMC 1.3 VVREF − V 0.2 Heating VILIMH 0.2 1.2 V Current-Limit Threshold Cooling VILIMC_TH VITEC = 0.5 V 1.98 2.0 2.02 V Heating VILIMH_TH VITEC = 2 V 0.48 0.5 0.52 V ILIM Input Current Heating IILIMH −0.2 +0.2 µA Cooling IILIMC Sourcing current 37.5 40 42.5 µA Cooling to Heating Current Detection ICOOL_HEAT_TH 40 mA Threshold TEC VOLTAGE LIMIT Voltage Limit Gain AVLIM (VDRL − VSFB)/VVLIM 2 V/V VLIM/SD Input Voltage Range1 VVLIMC, VVLIMH 0.2 VVDD/2 V VLIM/SD Input Current Cooling IILIMC VOUT2 < VVREF/2 −0.2 +0.2 µA Heating IILIMH VOUT2 > VVREF/2, sinking current 8 10 12 µA TEC CURRENT MEASUREMENT Current Sense Gain RCS 0.285 V/A Current Measurement Accuracy ILDR_ERROR 1 A ≤ ILDR ≤ 3 A 15 15 % ITEC Voltage Accuracy VITEC_AT_1_A Cooling, VVREF/2 + ILDR × RCS 1.493 1.535 1.577 V ITEC Voltage Output Range VITEC ITEC = 0 A 0 VVREF − V 0.05 ITEC Bias Voltage VITEC_B ILDR = 0 A 1.210 1.250 1.285 V Maximum ITEC Output Current IITEC −2 +2 mA TEC VOLTAGE MEASUREMENT Voltage Sense Gain AVTEC 0.24 0.25 0.26 V/V Rev. B | Page 5 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG PID CONTROL DIGITAL PID CONTROL POWERING THE CONTROLLER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8835 Devices TEMPERATURE LOCK INDICATOR SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION SIGNAL FLOW THERMISTOR SETUP THERMISTOR AMPLIFIER (CHOPPER 1) PID COMPENSATION AMPLIFIER (CHOPPER 2) MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Losses (PSW) Transition Losses (PTRAN) Linear Regulator Power Dissipation THERMAL CONSIDERATION PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE