Datasheet ADN8834 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Ultra compact 1.5 A Thermoelectric Cooler (TEC) Controller |
| 页数 / 页 | 27 / 10 — ADN8834. Data Sheet. VIN = 3.3V. VIN = 5V. %) R (. RRO E. TEC CURRENT. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 978 Kb |
| 文件语言 | 英语 |
ADN8834. Data Sheet. VIN = 3.3V. VIN = 5V. %) R (. RRO E. TEC CURRENT. ADI. RE E. PWM (TEC–). AG LT. VO –10 EC. LDO (TEC+). VT –15. –20. 0.5. 1.0. 1.5. 2.0
该数据表的模型线
文件文字版本
ADN8834 Data Sheet 20 VIN = 3.3V VIN = 5V 15 %) R ( 10 RRO E 5 NG TEC CURRENT ADI 0 4 RE E PWM (TEC–) –5 AG LT VO –10 EC LDO (TEC+) VT –15 1 –20
1
0.5 1.0 1.5 2.0 2.5
1 0 120
CH1 500mV BW CH2 500mV BW M10ms A CH4 –8mA TEC VOLTAGE (V)
12954-
CH3 300mA Ω BW T 5.4ms
12954- Figure 16. VTEC Voltage Reading Error vs. TEC Voltage in Cooling Mode Figure 19. Zero Crossing TEC Current Zoom in from Heating to Cooling
20 VIN = 3.3V VIN = 5V 15 %) R ( 10 RRO E 5 NG TEC CURRENT ADI 0 4 RE E PWM (TEC–) –5 AG LT VO –10 LDO (TEC+) EC VT –15 1 –20–2.5 –2.0 –1.5 –1.0 –0.5
014 120
CH1 500mV BW CH2 500mV BW M10ms A CH4 12mA TEC VOLTAGE (V)
12954-
CH3 200mA Ω BW T 5.4ms
12954- Figure 17. VTEC Voltage Reading Error vs. TEC Voltage in Heating Mode Figure 20. Zero Crossing TEC Current Zoom in from Cooling to Heating
LDO (TEC+) EN 3 PWM (TEC–) TEC CURRENT TEC CURRENT 4 4 LDO (TEC–) PWM (TEC+) 1
18
1
1
CH1 500mV B
121
B B W CH2 500mV BW M200ms A CH4 –108mA CH1 1V W CH2 1V W CH3 2V BW M20.0ms A CH3 800mV CH4 200mA Ω BW T –28.000ms CH4 500mA Ω B
12954-
W T 40ms
12954- Figure 18. Cooling to Heating Transition Figure 21. Typical Enable Waveforms in Cooling Mode, VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A Rev. B | Page 10 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Detailed Functional Block Diagram Theory of Operation Analog PID Control Digital PID Control Powering the Controller Enable and Shutdown Oscillator Clock Frequency External Clock Operation Connecting Multiple ADN8834 Devices Temperature Lock Indicator (LFCSP Only) Soft Start on Power-Up TEC Voltage/Current Monitor Voltage Monitor Current Monitor Maximum TEC Voltage Limit Using a Resistor Divider to Set the TEC Voltage Limit Maximum TEC Current Limit Using a Resistor Divider to Set the TEC Current Limit Applications Information Signal Flow Thermistor Setup Thermistor Amplifier (Chopper 1) PID Compensation Amplifier (Chopper 2) MOSFET Driver Amplifiers PWM Output Filter Requirements Inductor Selection Capacitor Selection Input Capacitor Selection Power Dissipation PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB Layout Guidelines Block Diagrams and Signal Flow Guidelines for Reducing Noise and Minimizing Power Loss General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components Example PCB Layout Using Two Layers Outline Dimensions Ordering Guide
1
0.5 1.0 1.5 2.0 2.5
1 0 120
CH1 500mV BW CH2 500mV BW M10ms A CH4 –8mA TEC VOLTAGE (V)
12954-
CH3 300mA Ω BW T 5.4ms
12954- Figure 16. VTEC Voltage Reading Error vs. TEC Voltage in Cooling Mode Figure 19. Zero Crossing TEC Current Zoom in from Heating to Cooling
20 VIN = 3.3V VIN = 5V 15 %) R ( 10 RRO E 5 NG TEC CURRENT ADI 0 4 RE E PWM (TEC–) –5 AG LT VO –10 LDO (TEC+) EC VT –15 1 –20–2.5 –2.0 –1.5 –1.0 –0.5
014 120
CH1 500mV BW CH2 500mV BW M10ms A CH4 12mA TEC VOLTAGE (V)
12954-
CH3 200mA Ω BW T 5.4ms
12954- Figure 17. VTEC Voltage Reading Error vs. TEC Voltage in Heating Mode Figure 20. Zero Crossing TEC Current Zoom in from Cooling to Heating
LDO (TEC+) EN 3 PWM (TEC–) TEC CURRENT TEC CURRENT 4 4 LDO (TEC–) PWM (TEC+) 1
18
1
1
CH1 500mV B
121
B B W CH2 500mV BW M200ms A CH4 –108mA CH1 1V W CH2 1V W CH3 2V BW M20.0ms A CH3 800mV CH4 200mA Ω BW T –28.000ms CH4 500mA Ω B
12954-
W T 40ms
12954- Figure 18. Cooling to Heating Transition Figure 21. Typical Enable Waveforms in Cooling Mode, VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A Rev. B | Page 10 of 27 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Detailed Functional Block Diagram Theory of Operation Analog PID Control Digital PID Control Powering the Controller Enable and Shutdown Oscillator Clock Frequency External Clock Operation Connecting Multiple ADN8834 Devices Temperature Lock Indicator (LFCSP Only) Soft Start on Power-Up TEC Voltage/Current Monitor Voltage Monitor Current Monitor Maximum TEC Voltage Limit Using a Resistor Divider to Set the TEC Voltage Limit Maximum TEC Current Limit Using a Resistor Divider to Set the TEC Current Limit Applications Information Signal Flow Thermistor Setup Thermistor Amplifier (Chopper 1) PID Compensation Amplifier (Chopper 2) MOSFET Driver Amplifiers PWM Output Filter Requirements Inductor Selection Capacitor Selection Input Capacitor Selection Power Dissipation PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB Layout Guidelines Block Diagrams and Signal Flow Guidelines for Reducing Noise and Minimizing Power Loss General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines Placing the Thermistor Amplifier and PID Components Example PCB Layout Using Two Layers Outline Dimensions Ordering Guide