Datasheet ADCMP603 (Analog Devices) - 5

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Data Sheet ADCMP603 TIMING INFORMATION
Figure 2 illustrates the ADCMP603 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V LATCH ENABLE tS tPL tH DIFFERENTIAL VIN VN ± VOS INPUT VOLTAGE VOD tPDL tPLOH Q OUTPUT 50% tF tPDH 50% Q OUTPUT tPLOL
023
tR
05915- Figure 2. System Timing Diagram
Table 2. Timing Descriptions Symbol Timing Description
tPDH Input to output high delay Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition. tPDL Input to output low delay Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition. tPLOH Latch enable to output high delay Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. tPLOL Latch enable to output low delay Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. tH Minimum hold time Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. tPL Minimum latch enable pulse width Minimum time that the latch enable signal must be high to acquire an input signal change. tS Minimum setup time Minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. tR Output rise time Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. tF Output fall time Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. VOD Voltage overdrive Difference between the input voltages VA and VB. Rev. A | Page 5 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL CHARACTERISTICS TIMING INFORMATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING TTL-/CMOS-COMPATIBLE OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS CROSSOVER BIAS POINT MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE