Preliminary Datasheet ADSP-21562, ADSP-21563, ADSP-21565 (Analog Devices) - 4

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ADSP-21562/21563/21565 Preliminary Technical Data SHARC PROCESSOR
The SHARC processor supports a modified Harvard architec- ture in combination with a hierarchical memory structure. L1 Figure 2 shows the SHARC processor integrates a SHARC+ memories typically operate at the full processor speed with little SIMD core, L1 memory crossbar, I/D cache controller, L1 mem- or no latency. ory blocks, and the master/slave ports. Figure 3 shows the SHARC+ SIMD core block diagram.
I-CACHE P-CACHE P-CA D-CA P-CACHE P-CA D-CA P-CACHE P-CA B0
S
RAM SIMD Processor B3 B2 B2 B1 B2 RAM RAM RAM RAM CCLK DOMAIN B3 (64) B2 (64) B1 (64) B0 (64) IO (32) IO (32) SLAVE PORT 1 INTERNAL MEMORY INTERFACE (IMIF) I/D CACHE CONTROL SLAVE IO (32) IO (32) PORT 2 (MDMA AND ACCELERATORS) SYSTEM FABRIC CORE SYSCLK MMR DM (64) PM (64) DOMAIN (32) DM (64) CMD (64) MASTER PM (64) PORT DATA ® SHARC+ SIMD CORE PS (64/48) CMI (64) MASTER PORT INSTRUCTION INTERRUPT SEC
Figure 2. SHARC Processor Block Diagram
L1 Memory
The SRAM of the processor can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, Figure 4 shows the ADSP-2156x memory map. The SHARC+ 106.7k words of 48-bit instructions (or 40-bit data), or combi- core has a tightly coupled L1 5 Mb SRAM. The SHARC+ core nations of different word sizes up to 5 Mb. All of the memory can access code and data in a single cycle from this memory can be accessed as 8-bit, 16-bit, 32-bit, 48-bit, or 64-bit words. space. Support of a 16-bit floating-point storage format doubles the In the SHARC+ core private address space, the core has L1 amount of data that can be stored on chip. memory. Conversion between the 32-bit floating-point and 16-bit float- SHARC+ core memory-mapped register (CMMR) address ing-point formats is performed in a single instruction. While space is 0x 0000 0000 through 0x0003 FFFF in normal word each memory block can store combinations of code and data, (32-bit). Each block can be configured for different combina- accesses are most efficient when one block stores data using the tions of code and data storage. Of the 5 Mb SRAM, up to DM bus for transfers, and the other block stores instructions 1024 Kb can be configured for data memory (DM), program and data using the PM bus for transfers. memory (PM), and instruction cache each. Each memory block Using the DM and PM buses, with each bus dedicated to a supports single-cycle, independent accesses by the core proces- memory block, assures single-cycle execution with two data sor and I/O processor. The memory architecture, in transfers. In this case, the instruction must be available in the combination with its separate on-chip buses, allows two data cache. The system configuration is flexible, but a typical config- transfers from the core and one from the direct memory access uration is 512 Kb DM, 128 Kb PM, and 128 Kb of instruction (DMA) engine in a single cycle. Rev. PrG | Page 4 of 95 | June 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Preliminary Specifications Preliminary Operating Conditions Preliminary Clock Related Operating Conditions Preliminary Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount 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