Preliminary Datasheet ADSP-21562, ADSP-21563, ADSP-21565 (Analog Devices) - 5

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Preliminary Technical Data ADSP-21562/21563/21565
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DEBUG FLAGS CEC BTB CONFLICT SIMD Core TRACE BP CACHE PM DATA 48 DMD/PMD 64 11-STAGE PROGRAM SEQUENCER PM ADDRESS 24 DAG1 DAG2 16 × 32 16 × 32 PM ADDRESS 32 SYSTEM DM ADDRESS 32 I/F TO PM DATA 64 IMIF USTAT PX DM DATA 64 PEx DATA PEy SWAP MULTIPLIER SHIFTER ALU DATA DATA ALU SHIFTER MULTIPLIER REGISTER REGISTER Rx Sx 16 × 40-BIT 16 × 40-BIT ASTATx ASTATy MRF MRB MSB MSF 80-BIT 80-BIT 80-BIT 80-BIT STYKx STYKy
Figure 3. SHARC+ SIMD Core Block Diagram cache, with the remaining L1 memory configured as SRAM.
Instruction and Data Cache
Each addressable memory space outside the L1 memory can be The ADSP-2156x processors also include a traditional instruc- accessed either directly or via cache. tion cache (I-cache) and two data caches (D-cache) The memory map in Table 2 gives the L1 memory address space (PM/DM caches) with parity support for all caches. These and shows multiple L1 memory blocks offering a configurable caches support one instruction access and two data accesses mix of SRAM and cache. over the DM and PM buses, per CCLK cycle. The cache control- lers automatically manage the configured L1 memory. The
L1 Master and Slave Ports
system can configure part of the L1 memory for automatic man- The SHARC+ core has two master/slave ports to and from the agement by the cache controllers. The sizes of these caches are system fabric. One master port fetches instructions. The second independently configurable from 0 Kb to a maximum of master port drives data to the system world. Slave port 1 1024 Kb each. The memory not managed by the cache control- together with slave port 2 (MDMA) run conflict free access to lers is directly addressable by the processors. The controllers the individual memory blocks. For the slave port addresses, ensure the data coherence between the two data caches. The refer to the L1 memory address map in Table 2. caches provide user-controllable features such as full and partial locking, range-bound invalidation, and flushing.
L1 On-Chip Memory Bandwidth System Event Controller (SEC) Input
The internal memory architecture allows programs to have four accesses at the same time to any of the four blocks, assuming no The output of the system event controller (SEC) controller is block conflicts. The total bandwidth is realized using both the forwarded to the core event controller (CEC) to respond DMD and PMD buses (2 × 64-bits CCLK speed and 2 × 32-bit directly to all unmasked system-based interrupts. The SEC also SYSCLK speed). supports nesting including various SEC interrupt channel Rev. PrG | Page 5 of 95 | June 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Preliminary Specifications Preliminary Operating Conditions Preliminary Clock Related Operating Conditions Preliminary Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Planned Automotive Production Products Planned Production Products Pre Release Products