Preliminary Datasheet ADSP-21562, ADSP-21563, ADSP-21565 (Analog Devices) - 6

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ADSP-21562/21563/21565 Preliminary Technical Data SHARC+ CORE ARCHITECTURE 0x FFFF FFFF RESERVED
The ADSP-2156x processors are code compatible at the assem-
0x C000 0000
bly level with the ADSP-2158x, ADSP-2157x, ADSP-2148x,
DMC0 (1GB) 0x 8000 0000
ADSP-2147x, ADSP-2146x, ADSP-2137x, ADSP-2136x, ADSP-
SPI2/OSPI0 FLASH ADDRESS SPACE (512MB)
2126x, ADSP-2116x, and with the first-generation ADSP-2106x
0x 6000 0000
SHARC processors.
0x 5000 0000
The ADSP-2156x processors share architectural features with
0x 4C00 0000
the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-214xx,
RESERVED
ADSP-2157x, ADSP-2158x, and ADSP-2116x SIMD SHARC
0x 4800 0000
processors, shown in Figure 3 and detailed in the following
0x 4400 0000
sections.
0x 4000 0000 Single-Instruction, Multiple Data (SIMD) Computational SYSTEM MMR 0x 3000 0000 Engine
The SHARC+ core contains two computational processing ele-
RESERVED
ments that operate as a single-instruction, multiple data (SIMD) engine.
0x 2840 0000 SHARC1 L1 ADDRESS SPACE VIA SLAVE 1/SLAVE 2 PORTS
The processing elements are referred to as PEx and PEy data
0x 2824 0000 UNIFIED
registers and each contain an arithmetic logic unit (ALU), mul-
RESERVED BYTE ADDRESS SPACE
tiplier, shifter, and register file. PEx is always active and PEy is
0x 202B FFFF
enabled by setting the PEYEN mode bit in the mode control
0x 2028 0000
register (MODE1).
RESERVED 0x 2011 8000
SIMD mode allows the processors to execute the same instruc-
L2 BOOT ROM 2 (0.25Mb)
tion in both processing elements, but each processing element
0x 2011 0000 L2 BOOT ROM 1 (0.25Mb)
operates on different data. This architecture efficiently executes
0x 2010 8000
math intensive DSP algorithms. In addition to all the features of
L2 BOOT ROM 0 (0.25Mb)
previous generation SHARC cores, the SHARC+ core also pro-
0x 2010 0000 L2 SRAM (8Mb)
vides a new and simpler way to execute an instruction only on
0x 2000 0000
the PEy data register.
RESERVED 0x 0039 FFFF
SIMD mode also affects the way data transfers between memory
L1 BLOCK 3 SRAM (1Mb)
and the processing elements because to sustain computational
0x 0038 0000 ADDRESS SP SHARC PRIV RESERVED
operation in the processing elements requires twice the data
0x 0031 FFFF
bandwidth. Therefore, entering SIMD mode doubles the band-
L1 BLOCK 2 SRAM (1Mb) 0x 0030 0000
width between memory and the processing elements. When
A A RESERVED C T E E
using the DAGs to transfer data in SIMD mode, two data values
0x 002E FFFF
transfer with each memory or register file access.
L1 BLOCK 1 SRAM (1.5Mb) 0x 002C 0000 RESERVED Independent Parallel Computation Units 0x 0026 FFFF L1 BLOCK 0 SRAM (1.5Mb)
Within each processing element is a set of pipelined computa-
0x 0024 0000
tional units. The computational units consist of a multiplier,
RESERVED/CORE MMRs/ OTHER MEMORY ALIASES 0x 0000 0000
arithmetic/logic unit (ALU), and shifter. These units are arranged in parallel, maximizing computational throughput. Figure 4. ADSP-2156x Memory Map These computational units support IEEE 32-bit single-precision floating-point, 40-bit extended-precision floating-point, IEEE arbitration options. For all SEC channels, the processor auto- 64-bit double-precision floating-point, and 32-bit fixed-point matically stacks the arithmetic status (ASTATx and ASTATy) data formats. registers and mode (MODE1) register in parallel with the inter- A multifunction instruction set supports parallel execution of rupt servicing. ALU and multiplier operations. In SIMD mode, the parallel
Core Memory-Mapped Registers (CMMR)
ALU and multiplier operations occur in both processing ele- ments per core. The core memory-mapped registers control the L1 instruction and data cache, BTB, parity error, system control, debug, and All processing operations take one cycle to complete. For all monitor functions. floating-point operations, the processor takes two cycles to complete in case of data dependency. Double-precision float- ing-point data take two to six cycles to complete. The processor stalls for the appropriate number of cycles for an interlocked pipeline plus data dependency check. Rev. PrG | Page 6 of 95 | June 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Preliminary Specifications Preliminary Operating Conditions Preliminary Clock Related Operating Conditions Preliminary Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount 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