Datasheet ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 (Analog Devices) - 8

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ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
• Arbitration logic to coordinate core and DMA transfers A set of programmable timing parameters is available to config- between internal and external memory over the external ure the SDRAM banks to support slower memory devices. Note port. that 32-bit wide devices are not supported on the SDRAM and Non-SDRAM external memory address space is shown in AMI interfaces. Table 5. The SDRAM controller address, data, clock, and control pins can drive loads up to distributed 30 pF. For larger memory sys-
Table 5. External Memory for Non-SDRAM Addresses
tems, the SDRAM controller external buffer timing should be selected and external buffering should be provided so that the
Size in
load on the SDRAM controller pins does not exceed 30 pF.
Bank Words Address Range
Note that the external memory bank addresses shown are for Bank 0 6M 0x0020 0000–0x007F FFFF normal-word (32-bit) accesses. If 48-bit instructions as well as Bank 1 8M 0x0400 0000–0x047F FFFF 32-bit data are both placed in the same external memory bank, Bank 2 8M 0x0800 0000–0x087F FFFF care must be taken while mapping them to avoid overlap. Bank 3 8M 0x0C00 0000–0x0C7F FFFF
SIMD Access to External Memory External Port
The SDRAM controller on the processor supports SIMD access on the 64-bit EPD (external port data bus) which allows access The external port provides a high performance, glueless inter- to the complementary registers on the PEy unit in the normal face to a wide variety of industry-standard memory devices. The word space (NW). This removes the need to explicitly access the external port, available on the 176-lead LQFP, may be used to complimentary registers when the data is in external SDRAM interface to synchronous and/or asynchronous memory devices memory. through the use of its separate internal memory controllers. The first is an SDRAM controller for connection of industry-stan-
VISA and ISA Access to External Memory
dard synchronous DRAM devices while the second is an The SDRAM controller on the ADSP-2148x processors sup- asynchronous memory controller intended to interface to a ports VISA code operation which reduces the memory load variety of memory devices. Four memory select pins enable up since the VISA instructions are compressed. Moreover, bus to four separate devices to coexist, supporting any desired com- fetching is reduced because, in the best case, one 48-bit fetch bination of synchronous and asynchronous device types. contains three valid instructions. Code execution from the tra-
Asynchronous Memory Controller
ditional ISA operation is also supported. Note that code execution is only supported from bank 0 regardless of The asynchronous memory controller provides a configurable VISA/ISA. Table 7 shows the address ranges for instruction interface for up to four separate banks of memory or I/O fetch in each mode. devices. Each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety
Table 7. External Bank 0 Instruction Fetch
of memory devices including SRAM, flash, and EPROM, as well as I/O devices that interface with standard memory control
Size in
lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3
Access Type Words Address Range
occupy a 8M word window in the processor’s address space but, if not fully populated, these windows are not made contiguous ISA (NW) 4M 0x0020 0000–0x005F FFFF by the memory controller logic. VISA (SW) 10M 0x0060 0000–0x00FF FFFF
SDRAM Controller
The SDRAM controller provides an interface of up to four sepa-
Pulse-Width Modulation
rate banks of industry-standard SDRAM devices at speeds up to The PWM module is a flexible, programmable, PWM waveform fSDCLK. Fully compliant with the SDRAM standard, each bank has generator that can be programmed to generate the required its own memory select line (MS0–MS3), and can be configured switching patterns for various applications related to motor and to contain between 4M bytes and 256M bytes of memory. engine control or audio power control. The PWM generator can SDRAM external memory address space is shown in Table 6. generate either center-aligned or edge-aligned PWM wave- NOTE: this feature is not available on the ADSP-21486 model. forms. In addition, it can generate complementary signals on two outputs in paired mode or independent signals in non-
Table 6. External Memory for SDRAM Addresses
paired mode (applicable to a single group of four PWM waveforms).
Size in Bank Words Address Range
The entire PWM module has four groups of four PWM outputs Bank 0 62M 0x0020 0000–0x03FF FFFF generating 16 PWM outputs in total. Each PWM group pro- duces two pairs of PWM signals on the four PWM outputs. Bank 1 64M 0x0400 0000–0x07FF FFFF Bank 2 64M 0x0800 0000–0x0BFF FFFF Bank 3 64M 0x0C00 0000–0x0FFF FFFF Rev. H | Page 8 of 71 | February 2020 Document Outline Features Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Timer Data Register File Context Switch Universal Registers Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Variable Instruction Set Architecture (VISA) On-Chip Memory ROM Based Security On-Chip Memory Bandwidth Family Peripheral Architecture External Memory External Port Asynchronous Memory Controller SDRAM Controller SIMD Access to External Memory VISA and ISA Access to External Memory Pulse-Width Modulation MediaLB Digital Applications Interface (DAI) Serial Ports (SPORTs) S/PDIF-Compatible Digital Audio Receiver/Transmitter Asynchronous Sample Rate Converter (SRC) Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface (SPI) UART Port Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA FFT Accelerator FIR Accelerator IIR Accelerator Watchdog Timer System Design Program Booting Power Supplies Static Voltage Scaling (SVS) Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Maximum Power Dissipation Timing Specifications Core Clock Requirements Voltage Controlled Oscillator (VCO) Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Watchdog Timer Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) AMI Read AMI Write Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Media Local Bus Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing 2-Wire Interface (TWI)—Receive and Transmit Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics Thermal Diode 88-Lead LFCSP_VQ Lead Assignment 100-Lead LQFP_EP Lead Assignment 176-Lead LQFP_EP Lead Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide