Datasheet ADSP-TS101S (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | TigerSHARC Embedded Processor |
| 页数 / 页 | 45 / 2 — ADSP-TS101S. TABLE OF CONTENTS. REVISION HISTORY. 4/21—Rev. C to Rev. D |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
ADSP-TS101S. TABLE OF CONTENTS. REVISION HISTORY. 4/21—Rev. C to Rev. D
该数据表的模型线
文件文字版本
link to page 1 link to page 1 link to page 2 link to page 2 link to page 3 link to page 4 link to page 4 link to page 4 link to page 5 link to page 5 link to page 6 link to page 6 link to page 7 link to page 9 link to page 9 link to page 9 link to page 9 link to page 9 link to page 10 link to page 10 link to page 10 link to page 10 link to page 11 link to page 11 link to page 11 link to page 12 link to page 12 link to page 12 link to page 19 link to page 20 link to page 20 link to page 20 link to page 21 link to page 21 link to page 21 link to page 32 link to page 34 link to page 36 link to page 37 link to page 43 link to page 44 link to page 45 link to page 20 link to page 20 link to page 44 link to page 44 link to page 44 link to page 45 link to page 43 link to page 43 link to page 43
ADSP-TS101S TABLE OF CONTENTS
Features ... 1 Designing an Emulator-Compatible Benefits ... 1 DSP Board (Target) .. 11 Table of Contents ... 2 Additional Information .. 11 Revision History .. 2 Pin Function Descriptions .. 12 General Description ... 3 Pin States at Reset .. 12 Dual Compute Blocks .. 4 Pin Definitions ... 12 Data Alignment Buffer (DAB) .. 4 Strap Pin Function Descriptions .. 19 Dual Integer ALUs (IALUs) .. 4 Specifications .. 20 Program Sequencer ... 5 Operating Conditions ... 20 On-Chip SRAM Memory .. 5 Electrical Characteristics ... 20 External Port Absolute Maximum Ratings ... 21 (Off-Chip Memory/Peripherals Interface) .. 6 ESD Caution .. 21 DMA Controller ... 7 Timing Specifications ... 21 Link Ports ... 9 Output Drive Currents ... 32 Timer and General-Purpose I/O ... 9 Test Conditions .. 34 Reset and Booting ... 9 Environmental Conditions .. 36 Low Power Operation .. 9 PBGA Pin Configurations .. 37 Clock Domains .. 9 Outline Dimensions .. 43 Output Pin Drive Strength Control ... 10 Surface-Mount Design ... 44 Power Supplies ... 10 Ordering Guide ... 45 Filtering Reference Voltage and Clocks .. 10 Development Tools ... 10
REVISION HISTORY 4/21—Rev. C to Rev. D
Changes to Operating Conditions .. 20 Changes to Electrical Characteristics ... 20 Removed Package Information section Changes to package diagram per PCN # 20_0165 484-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (B-484-1) Dimen- sions shown in millimeters ... 43 Changes to package diagram per PCN # 20_0165 625-Ball Plas- tic Ball Grid Array [PBGA] (B-625-2) Dimensions shown in millimeters ... 44 Changes to Ordering Guide .. 45 Rev. D | Page 2 of 45 | April 2021 Document Outline TigerSHARC Embedded Processor Features Benefits Table of Contents Revision History General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction Set On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA Controller Link Ports Timer and General-Purpose I/O Reset and Booting Low Power Operation Clock Domains Output Pin Drive Strength Control Power Supplies Filtering Reference Voltage and Clocks Development Tools Designing an Emulator-Compatible DSP Board (Target) Additional Information Pin Function Descriptions Pin States at Reset Pin Definitions Strap Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications General AC Timing Link Ports Data Transfer and Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics PBGA Pin Configurations Outline Dimensions Surface-Mount Design Ordering Guide
ADSP-TS101S TABLE OF CONTENTS
Features ... 1 Designing an Emulator-Compatible Benefits ... 1 DSP Board (Target) .. 11 Table of Contents ... 2 Additional Information .. 11 Revision History .. 2 Pin Function Descriptions .. 12 General Description ... 3 Pin States at Reset .. 12 Dual Compute Blocks .. 4 Pin Definitions ... 12 Data Alignment Buffer (DAB) .. 4 Strap Pin Function Descriptions .. 19 Dual Integer ALUs (IALUs) .. 4 Specifications .. 20 Program Sequencer ... 5 Operating Conditions ... 20 On-Chip SRAM Memory .. 5 Electrical Characteristics ... 20 External Port Absolute Maximum Ratings ... 21 (Off-Chip Memory/Peripherals Interface) .. 6 ESD Caution .. 21 DMA Controller ... 7 Timing Specifications ... 21 Link Ports ... 9 Output Drive Currents ... 32 Timer and General-Purpose I/O ... 9 Test Conditions .. 34 Reset and Booting ... 9 Environmental Conditions .. 36 Low Power Operation .. 9 PBGA Pin Configurations .. 37 Clock Domains .. 9 Outline Dimensions .. 43 Output Pin Drive Strength Control ... 10 Surface-Mount Design ... 44 Power Supplies ... 10 Ordering Guide ... 45 Filtering Reference Voltage and Clocks .. 10 Development Tools ... 10
REVISION HISTORY 4/21—Rev. C to Rev. D
Changes to Operating Conditions .. 20 Changes to Electrical Characteristics ... 20 Removed Package Information section Changes to package diagram per PCN # 20_0165 484-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (B-484-1) Dimen- sions shown in millimeters ... 43 Changes to package diagram per PCN # 20_0165 625-Ball Plas- tic Ball Grid Array [PBGA] (B-625-2) Dimensions shown in millimeters ... 44 Changes to Ordering Guide .. 45 Rev. D | Page 2 of 45 | April 2021 Document Outline TigerSHARC Embedded Processor Features Benefits Table of Contents Revision History General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction Set On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA Controller Link Ports Timer and General-Purpose I/O Reset and Booting Low Power Operation Clock Domains Output Pin Drive Strength Control Power Supplies Filtering Reference Voltage and Clocks Development Tools Designing an Emulator-Compatible DSP Board (Target) Additional Information Pin Function Descriptions Pin States at Reset Pin Definitions Strap Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications General AC Timing Link Ports Data Transfer and Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics PBGA Pin Configurations Outline Dimensions Surface-Mount Design Ordering Guide