Datasheet ADSP-TS101S (Analog Devices) - 10

link to page 12 link to page 18 link to page 18 link to page 18 link to page 32 link to page 32 link to page 10
ADSP-TS101S
ates CCLK, which is phase-locked. The LCLKRAT pins
FILTERING REFERENCE VOLTAGE AND CLOCKS
define the clock multiplication of LCLK to CCLK (see Figure 6 shows a possible circuit for filtering V Table 4). The link port clock is generated from CCLK via a REF, SCLK_N, and LCLK_N. This circuit provides the reference voltage for the software programmable divisor. RESET must be asserted switching voltage, system clock, and local clock references. until LCLK is stable and within specification for at least 2 ms. This applies to power-up as well as any dynamic modification of LCLK after power-up. Dynamic modifica-
VDD_IO VREF
tion may include LCLK going out of specification as long as RESET is asserted.
SCLK_N R1
Connecting SCLK and LCLK to the same clock source is a
LCLK_N
requirement for the device. Using an integer clock multiplica-
R2 C1 C2
tion value provides predictable cycle-by-cycle operation, a requirement of fault-tolerant systems and some multiprocessing
VSS
systems.
R1: 2k
⍀
SERIES RESISTOR
Noninteger values are completely functional and acceptable for
R2: 1.67k
⍀
SERIES RESISTOR C1: 1
␮
F CAPACITOR (SMD)
applications that do not require predictable cycle-by-cycle
C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS
operation. Figure 6. VREF, SCLK_N, and LCLK_N Filter
OUTPUT PIN DRIVE STRENGTH CONTROL
Pins CONTROLIMP2–0 and DS2–0 work together to control
DEVELOPMENT TOOLS
the output drive strength of two groups of pins, the The ADSP-TS101S is supported with a complete set of Address/Data/Control pin group and the Link pin group. CON- CROSSCORE®† software and hardware development tools, TROLIMP2–0 independently configures the two pin groups to including Analog Devices emulators and VisualDSP++®‡ devel- the maximum drive strength or to a digitally controlled drive opment environment. The same emulator hardware that strength that is selectable by the DS2–0 pins (see Table 13 on supports other TigerSHARC processors also fully emulates the Page 18). If the digitally controlled drive strength is selected for ADSP-TS101S. a pin group, the DS2–0 pins determine one of eight strength lev- els for that group (see Table 14 on Page 18). The drive strength The VisualDSP++ project management environment lets pro- selected varies the slew rate of the driver. Drive strength 0 grammers develop and debug an application. This environment (DS2–0 = 000) is the weakest and slowest slew rate. Drive includes an easy to use assembler (which is based on an alge- strength 7 (DS2–0 = 111) is the strongest and fastest slew rate. braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-level simulator, a C/C++ The stronger drive strengths are useful for high frequency compiler, and a C/C++ run-time library that includes DSP and switching while the lower strengths may allow use of a relaxed mathematical functions. A key point for these tools is C/C++ design methodology. The strongest drive strengths have a larger code efficiency. The compiler has been developed for efficient di/dt and thus require more attention to signal integrity issues translation of C/C++ code to DSP assembly. The DSP has archi- such a ringing, reflections and coupling. Also, a larger di/dt can tectural features that improve the efficiency of compiled C/C++ increase external supply rail noise, which impacts power supply code. and power distribution design. The VisualDSP++ debugger has a number of important fea- The drive strengths for the EMU, CPA, and DPA pins are not tures. Data visualization is enhanced by a plotting package that controllable and are fixed to the maximum level. offers a significant level of flexibility. This graphical representa- For drive strength calculation, see Output Drive Currents on tion of user data enables the programmer to quickly determine Page 32. the performance of an algorithm. As algorithms grow in com- plexity, this capability can have increasing significance on the
POWER SUPPLIES
designer’s development schedule, increasing productivity. Sta- The ADSP-TS101S has separate power supply connections for tistical profiling enables the programmer to nonintrusively poll internal logic (V the processor as it is running the program. This feature, unique DD), analog circuits (VDD_A), and I/O buffer (V to VisualDSP++, enables the software developer to passively DD_IO) power supply. The internal (VDD) and analog (VDD_A) supplies must meet the 1.2 V requirement. The I/O buffer gather important code execution metrics without interrupting (V the real-time characteristics of the program. Essentially, the DD_IO) supply must meet the 3.3 V requirement. developer can identify bottlenecks in software quickly and The analog supply (VDD_A) powers the clock generator PLLs. To efficiently. By using the profiler, the programmer can focus on produce a stable clock, systems must provide a clean power sup- those areas in the program that impact performance and take ply to power input VDD_A. Designs must pay critical attention to corrective action. bypassing the VDD_A supply. The required power-on sequence for the DSP is to provide VDD (and VDD_A) before VDD_IO. † CROSSCORE is a registered trademark of Analog Devices, Inc. ‡ VisualDSP++ is a registered trademark of Analog Devices, Inc. Rev. D | Page 10 of 45 | April 2021 Document Outline TigerSHARC Embedded Processor Features Benefits Table of Contents Revision History General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction Set On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA Controller Link Ports Timer and General-Purpose I/O Reset and Booting Low Power Operation Clock Domains Output Pin Drive Strength Control Power Supplies Filtering Reference Voltage and Clocks Development Tools Designing an Emulator-Compatible DSP Board (Target) Additional Information Pin Function Descriptions Pin States at Reset Pin Definitions Strap Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications General AC Timing Link Ports Data Transfer and Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics PBGA Pin Configurations Outline Dimensions Surface-Mount Design Ordering Guide