Datasheet ADSP-TS101S (Analog Devices) - 9

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ADSP-TS101S LINK PORTS
After reset, the ADSP-TS101S has four boot options for begin- ning operation: The DSP’s four link ports provide additional 8-bit bidirectional I/O capability. With the ability to operate at a double data rate— • Boot from EPROM. The DSP defaults to EPROM booting latching data on both the rising and falling edges of the clock— when the BMS pin strap option is set low. See Strap Pin running at 125 MHz, each link port can support up to Function Descriptions on Page 19. 250M bytes per second, for a combined maximum throughput • Boot by an external master (host or another ADSP- of 1G bytes per second. TS101S). Any master on the cluster bus can boot the The link ports provide an optional communications channel ADSP-TS101S through writes to its internal memory or that is useful in multiprocessor systems for implementing point- through autoDMA. to-point interprocessor communications. Applications can also • Boot by link port. All four receive link DMA channels are use the link ports for booting. initialized after reset to transfer a 256-word block to inter- Each link port has its own double-buffered input and output nal memory address 0 to 255, and to issue an interrupt at registers. The DSP’s core can write directly to a link port’s trans- the end of the block (similar to EP DMA). The correspond- mit register and read from a receive register, or the DMA ing DMA interrupts are set to address zero (0). controller can perform DMA transfers through eight (four • No boot—Start running from an external memory. Using transmit and four receive) dedicated link port DMA channels. the “no boot” option, the ADSP-TS101S must start running Each link port has three signals that control its operation. from an external memory, caused by asserting one of the LxCLKOUT and LxCLKIN implement clock/acknowledge IRQ3–0 interrupt signals. handshaking. LxDIR indicates the direction of transfer and is The ADSP-TS101S core always exits from reset in the idle state used only when buffering the LxDAT signals. An example appli- and waits for an interrupt. Some of the interrupts in the inter- cation would be using differential low-swing buffers for long rupt vector table are initialized and enabled after reset. twisted-pair wires. LxDAT provides the 8-bit data bus input/output.
LOW POWER OPERATION
Applications can program separate error detection mechanisms The ADSP-TS101S can enter a low power sleep mode in which for transmit and receive operations (applications can use the its core does not execute instructions, reducing power con- checksum mechanism to implement consecutive link port sumption to a minimum. The ADSP-TS101S exits sleep mode transfers), the size of data packets, and the speed at which bytes when it senses a falling edge on any of its IRQ3–0 interrupt are transmitted. inputs. The interrupt, if enabled, causes the ADSP-TS101S to Under certain conditions, the link port receiver can initiate a execute the corresponding interrupt service routine. This fea- token switch to reverse the direction of transfer; the transmitter ture is useful for systems that require a low power standby becomes the receiver and vice versa. mode.
TIMER AND GENERAL-PURPOSE I/O CLOCK DOMAINS
The ADSP-TS101S has a timer pin (TMR0E) that generates out- As shown in Figure 5, the ADSP-TS101S has two clock inputs, put when a programmed timer counter has expired. Also, the SCLK (system clock) and LCLK (local clock). DSP has four programmable general-purpose I/O pins (FLAG3–0) that can function as either single-bit input or out-
SCLK_P DLL EXTERNAL INTERFACE
put. As outputs, these pins can signal peripheral devices; as inputs, they can provide the test for conditional branching.
CCLK LCLK_P DLL PLL (INSTRUCTION RATE) RESET AND BOOTING LxCLKOUT/LxCLKIN LCLKRATx DL /L L R (LINK PORT RATE)
The ADSP-TS101S has two levels of reset (see reset specifica-
SPD BITS,
tions Page 23):
LCTLx REGISTER
• Power-up reset—after power-up of the system, and strap Figure 5. Clock Domains options are stable, the RESET pin must be asserted (low). • Normal reset—for any resets following the power-up reset These inputs drive its two major clock domains: sequence, the RESET pin must be asserted. • SCLK (system clock). Provides clock input for the external The DSP can be reset internally (core reset) by setting the bus interface and defines the ac specification reference for SWRST bit in SQCTL. The core is reset, but not the external the external bus signals. The external bus interface runs at port or I/O. 1 the SCLK frequency. A DLL locks internal SCLK to SCLK input. • LCLK (local clock). Provides clock input to the internal clock driver, CCLK, which is the internal clock for the core, internal buses, memory, and link ports. The instruction execution rate is equal to CCLK. A PLL from LCLK gener- Rev. D | Page 9 of 45 | April 2021 Document Outline TigerSHARC Embedded Processor Features Benefits Table of Contents Revision History General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction Set On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA Controller Link Ports Timer and General-Purpose I/O Reset and Booting Low Power Operation Clock Domains Output Pin Drive Strength Control Power Supplies Filtering Reference Voltage and Clocks Development Tools Designing an Emulator-Compatible DSP Board (Target) Additional Information Pin Function Descriptions Pin States at Reset Pin Definitions Strap Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications General AC Timing Link Ports Data Transfer and Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics PBGA Pin Configurations Outline Dimensions Surface-Mount Design Ordering Guide