Datasheet ADSP-TS101S (Analog Devices) - 3

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ADSP-TS101S GENERAL DESCRIPTION
The ADSP-TS101S TigerSHARC® processor is an ultrahigh per- 2 This value is for six iterations of the algorithm. For eight iterations of the turbo formance, Static SuperscalarTM †processor optimized for large decoder, this benchmark is 67 MIPS. 3 Adaptive multi rate (AMR) signal processing tasks and communications infrastructure. The 4 Megachips per second (Mcps) DSP combines very wide memory widths with dual computa- tion blocks—supporting 32- and 40-bit floating-point and 8-, The ADSP-TS101S is code compatible with the other 16-, 32-, and 64-bit fixed-point processing—to set a new stan- TigerSHARC processors. dard of performance for digital signal processors. The TigerSHARC processor’s Static Superscalar architecture lets the The Functional Block Diagram on Page 1 shows the processor’s processor execute up to four instructions each cycle, performing architectural blocks. These blocks include: 24 fixed-point (16-bit) operations or six floating-point • Dual compute blocks, each consisting of an ALU, multi- operations. plier, 64-bit shifter, and 32-word register file and associated Three independent 128-bit-wide internal data buses, each data alignment buffers (DABs) connecting to one of the three 2M bit memory banks, enable • Dua l integer ALUs (IALUs) , each with its own 31-word quad word data, instruction, and I/O accesses and provide register file for data addressing 14.4G bytes per second of internal memory bandwidth. Operat- • A program sequencer with instruction alignment buffer ing at 300 MHz, the ADSP-TS101S processor’s core has a 3.3 ns (IAB), branch target buffer (BTB), and interrupt controller instruction cycle time. Using its single-instruction, multiple- data (SIMD) features, the ADSP-TS101S can perform 2.4 billion • Three 128-bit internal data buses, each connecting to one 40-bit MACs or 600 million 80-bit MACs per second. Table 1 of three 2M bit memory banks and Table 2 show the DSP’s performance benchmarks. • On-chip SRAM (6M bit) • An external port that provides the interface to host proces-
Table 1. General-Purpose Algorithm Benchmarks
sors, multiprocessing space (DSPs), off-chip memory-
at 300 MHz
mapped peripherals, and external SRAM and SDRAM
Clock
• A 14-channel DMA controller
Benchmark Speed Cycles
• Four link ports 32-bit algorithm, 600 million MACs/s peak performance • Two 64-bit interval timers and timer expired pin 1024 point complex FFT (Radix 2) 32.78 μs 9,835 • A 1149.1 IEEE compliant JTAG test access port for on-chip 50-tap FIR on 1024 input 91.67 μs 27,500 emulation Single FIR MAC 1.83 ns 0.55 Figure 2 shows a typical single-processor system with external 16-bit algorithm, 2.4 billion MACs/s peak performance SDRAM. Figure 4 on Page 8 shows a typical multiprocessor 256 point complex FFT (Radix 2) 3.67 μs 1,100 system. 50-tap FIR on 1024 input 24.0 μs 7,200 The TigerSHARC processor uses a Static Superscalar architec- Single FIR MAC 0.47 ns 0.14 ture. This architecture is superscalar in that the ADSP-TS101S Single complex FIR MAC 1.9 ns 0.57 processor’s core can execute simultaneously from one to four I/O DMA transfer rate 32-bit instructions encoded in a very large instruction word External port 800M bytes/s n/a (VLIW) instruction line using the DSP’s dual compute blocks. Because the DSP does not perform instruction reordering at Link ports (each) 250M bytes/s n/a runtime—the programmer selects which operations will execute in parallel prior to runtime—the order of instructions is static.
Table 2. 3G Wireless Algorithm Benchmarks
With few exceptions, an instruction line, whether it contains
Execution
one, two, three, or four 32-bit instructions, executes with a
Benchmark (MIPS)1
throughput of one cycle in an eight-deep processor pipeline. Turbo decode 51 MIPS2 For optimal DSP program execution, programmers must follow 384 kbps data channel the DSP’s set of instruction parallelism rules when encoding an Viterbi decode 0.86 MIPS instruction line. In general, the selection of instructions that the 12.2 kbps AMR3 voice channel DSP can execute in parallel each cycle depends on the instruc- Complex correlation 0.27 MIPS tion line resources each instruction requires and on the source 3.84 Mcps4 with a spreading factor of 256 and destination registers used in the instructions. The program- 1 mer has direct control of three core components—the IALUs, The execution speed is in instruction cycles per second. the compute blocks, and the program sequencer. † Static Superscalar is a trademark of Analog Devices, Inc. Rev. D | Page 3 of 45 | April 2021 Document Outline TigerSHARC Embedded Processor Features Benefits Table of Contents Revision History General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction Set On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface DMA Controller Link Ports Timer and General-Purpose I/O Reset and Booting Low Power Operation Clock Domains Output Pin Drive Strength Control Power Supplies Filtering Reference Voltage and Clocks Development Tools Designing an Emulator-Compatible DSP Board (Target) Additional Information Pin Function Descriptions Pin States at Reset Pin Definitions Strap Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications General AC Timing Link Ports Data Transfer and Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics PBGA Pin Configurations Outline Dimensions Surface-Mount Design Ordering Guide