Datasheet ADGS1208, ADGS1209 (Analog Devices) - 9
| 制造商 | Analog Devices |
| 描述 | SPI Interface, Low CON and QINJ, ±15 V/+12 V, 1.8 V Logic Control, 8:1/Dual 4:1 Mux Switches |
| 页数 / 页 | 33 / 9 — Data Sheet. ADGS1208/. ADGS1209. TIMING CHARACTERISTICS. Table 5. … |
| 文件格式/大小 | PDF / 676 Kb |
| 文件语言 | 英语 |
Data Sheet. ADGS1208/. ADGS1209. TIMING CHARACTERISTICS. Table 5. Parameter. Limit. Unit. Test Conditions/Comments. Timing Diagrams. SCLK
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Data Sheet ADGS1208/ ADGS1209 TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested.
Table 5. Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTERISTICS t1 20 ns min SCLK or CNV period t2 8 ns min SCLK or CNV high pulse width t3 8 ns min SCLK or CNV low pulse width t4 10 ns min CS falling edge to SCLK or CNV active edge t5 6 ns min Data setup time t6 8 ns min Data hold time t7 10 ns min SCLK or CNV active edge to CS rising edge t8 20 ns max CS falling edge to SDO data available t 1 9 20 ns max SCLK falling edge to SDO data available t10 20 ns max CS rising edge to SDO returns to high impedance t11 20 ns min CS high time between SPI commands t12 8 ns min CS falling edge to SCLK or CNV edge rejection t13 8 ns min CS rising edge to SCLK or CNV edge rejection 1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Timing Diagrams t1 SCLK t2 t t t7 4 3 CS t t 6 5 SDI R/W A6 A5 D2 D1 D0 t t 9 10 SDO 0 0 1 D2 D1 D0
102
t8
16724- Figure 3. Address Mode Timing Diagram Rev. 0 | Page 9 of 33 Document Outline Features Applications General Description Functional Block Diagrams Product Highlights Revision History Specifications ±15 V Dual Supply 12 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error Detection Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Round Robin Mode General-Purpose Outputs Applications Information Digital Input Buffers Settling Time Power Supply Rails Power Supply Recommendations Register Summaries Register Details Switch Data Register Error Configuration Register Error Flags Register Burst Enable Register Round Robin Enable Register Round Robin Channel Configuration Register CNV Edge Select Register Software Reset Register Outline Dimensions Ordering Guide
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization, not production tested.
Table 5. Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTERISTICS t1 20 ns min SCLK or CNV period t2 8 ns min SCLK or CNV high pulse width t3 8 ns min SCLK or CNV low pulse width t4 10 ns min CS falling edge to SCLK or CNV active edge t5 6 ns min Data setup time t6 8 ns min Data hold time t7 10 ns min SCLK or CNV active edge to CS rising edge t8 20 ns max CS falling edge to SDO data available t 1 9 20 ns max SCLK falling edge to SDO data available t10 20 ns max CS rising edge to SDO returns to high impedance t11 20 ns min CS high time between SPI commands t12 8 ns min CS falling edge to SCLK or CNV edge rejection t13 8 ns min CS rising edge to SCLK or CNV edge rejection 1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Timing Diagrams t1 SCLK t2 t t t7 4 3 CS t t 6 5 SDI R/W A6 A5 D2 D1 D0 t t 9 10 SDO 0 0 1 D2 D1 D0
102
t8
16724- Figure 3. Address Mode Timing Diagram Rev. 0 | Page 9 of 33 Document Outline Features Applications General Description Functional Block Diagrams Product Highlights Revision History Specifications ±15 V Dual Supply 12 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error Detection Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Round Robin Mode General-Purpose Outputs Applications Information Digital Input Buffers Settling Time Power Supply Rails Power Supply Recommendations Register Summaries Register Details Switch Data Register Error Configuration Register Error Flags Register Burst Enable Register Round Robin Enable Register Round Robin Channel Configuration Register CNV Edge Select Register Software Reset Register Outline Dimensions Ordering Guide