Datasheet BlueNRG-LPS (STMicroelectronics) - 7

BlueNRG-LPS Security and safety 1.3.5 Memory protection unit (MPU)
The MPU is used to manage accesses to memory to prevent one task from accidentally corrupting the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area settings, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it.
1.4 Security and safety
The BlueNRG-LPS contains many security blocks for the BLE and the host application. It includes: • Flash read/write protection over accidental and intentional actions • As protection against potential hacker attacks, the SWD access can be disabled • Secure bootloader (refer to the dedicated application note AN5471) • Customer storage of the BLE keys • True random number generator (RNG) • Public key accelerator (PKA) including: – Modular arithmetic including exponentiation with maximum modulo size of 3136 bits – Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA verification with maximum modulo size of 521 bits • Cyclic redundancy check calculation unit (CRC)
1.5 RF subsystem
The BlueNRG-LPS embeds an ultra-low power radio, compliant with Bluetooth® Low Energy (BLE) specification. The BLE features 1 Mbps and 2 Mbps transfer rates as well as long range options (125 kbps, 500 kbps), supports multiple roles simultaneously acting at the same time as Bluetooth® Low Energy sensor and hub device. The BLE protocol stack is implemented by an efficient system partitioned as follows: • Hardware part: BlueCore handling time critical and time consuming BLE protocol parts • Firmware part: Arm® Cortex®-M0+ core handling non time critical BLE protocol parts
1.5.1 RF front-end block diagram
The RF front end is based on a direct modulation of the carrier in TX, and uses a low IF architecture in RX mode. Thanks to an internal transformer with RF pins, the circuit directly interfaces the antenna (single ended connection, impedance close to 50 Ω). The natural band pass behavior of the internal transformer simplifies outside circuitry aimed at harmonic filtering and out of band interferer rejection. In transmit mode, the maximum output power is user selectable through the programmable LDO voltage of the power amplifier. A linearized, smoothed analog control offers a clean power ramp-up. In receive mode the circuit can be used in standard high performance or in reduced power consumption (user programmable). The automatic gain control (AGC) is able to reduce the chain gain at both RF and IF locations, for an optimized interferer rejection. Thanks to the use of complex filtering and highly accurate I/Q architecture, high sensitivity, and excellent linearity can be achieved.
DS13819
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Rev 2 page 7/63
Document Outline Features Applications Description 1 Functional overview 1.1 System architecture 1.2 Arm® Cortex®-M0+ core with MPU 1.3 Memories 1.3.1 Embedded Flash memory 1.3.2 Embedded SRAM 1.3.3 Embedded ROM 1.3.4 Embedded OTP 1.3.5 Memory protection unit (MPU) 1.4 Security and safety 1.5 RF subsystem 1.5.1 RF front-end block diagram 1.6 Power supply management 1.6.1 SMPS step-down regulator 1.6.2 Power supply schemes 1.6.3 Linear voltage regulators 1.6.4 Power supply supervisor 1.7 Operating modes 1.7.1 RUN mode 1.7.2 DEEPSTOP mode 1.7.3 SHUTDOWN mode 1.8 Reset management 1.9 Clock management 1.10 Boot mode 1.11 Embedded UART bootloader 1.12 General purpose inputs/outputs (GPIO) 1.13 Direct memory access (DMA) 1.14 Nested vectored interrupt controller (NVIC) 1.15 Analog digital converter (ADC) 1.15.1 Temperature sensor 1.16 True random number generator (RNG) 1.17 Timers and watchdog 1.17.1 General-purpose timers (TIM2, TIM16, TIM17) 1.17.2 Independent watchdog (IWDG) 1.17.3 SysTick timer 1.18 Real-time clock (RTC) 1.19 Inter-integrated circuit interface (I2C) 1.20 Universal synchronous/asynchronous receiver transmitter (USART) 1.21 LPUART 1.22 Serial peripheral interface (SPI) 1.23 Inter-IC sound (I2S) 1.24 Serial wire debug port 1.25 TX and RX event alert 1.26 Direction finding 2 Pinouts and pin description 3 Memory mapping 4 Application circuits 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Loading capacitor 5.1.5 Pin input voltage 5.2 Absolute maximum ratings 5.3 Operating conditions 5.3.1 Summary of main performance 5.3.2 General operating conditions 5.3.3 RF general characteristics 5.3.4 RF transmitter characteristics 5.3.5 RF receiver characteristics 5.3.6 Embedded reset and power control block characteristics 5.3.7 Supply current characteristics 5.3.8 Wake-up time from low power modes 5.3.9 High speed crystal requirements 5.3.10 Low speed crystal requirements 5.3.11 High speed ring oscillator characteristics 5.3.12 Low speed ring oscillator characteristics 5.3.13 PLL characteristics 5.3.14 Flash memory characteristics 5.3.15 Electrostatic discharge (ESD) 5.3.16 I/O port characteristics 5.3.17 RSTN pin characteristics 5.3.18 ADC characteristics 5.3.19 Temperature sensor characteristics 5.3.20 Timer characteristics 5.3.21 I2C interface characteristics 5.3.22 SPI characteristics 6 Package information 6.1 QFN32 (5x5x0.9, pitch 0.5 mm) package information 6.2 WLCSP36 package information 6.3 Thermal characteristics 7 Ordering information Revision history