Preliminary Datasheet EPC23102 (Efficient Power Conversion) - 5

eGaN® FET DATASHEET
EPC23102
Electrical Characteristics
(continued)
Electrical Characteristics (continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Dynamic Characteristics (Logic Input to Output Switching Node)
See Figure 3a and 3b for Timing Diagram and Test Circuit) t_delayHS_on High-Side On Propagation Delay SW = 0 V and HS FET Turn-On 20 t_delayLS_on Low-Side On Propagation Delay SW = 48 V and LS FET Turn-On 20 t_delayHS_off High-Side Off Propagation Delay SW = 48 V and HS FET Turn-Off 20 t_delayLS_off Low-Side Off Propagation Delay SW = 0 V and LS FET Turn-Off 20 t_matchon Delay Matching LSoff to HSon LS Turn-Off to HS Turn-On 0 ns t_matchoff Delay Matching HSoff to LSon HS Turn-Off to LS Turn-On 0 t_riseSW_HS0 SW Rise Time at High Side FET Turn-On HS Turn-On Buck Mode, 0 V to 48 V, RBOOT = 0 Ω, ILoad = 5 A 1.5 t_rise (Buck Mode, Hard Switching) SW_HS1 HS Turn-On Buck Mode, 0 V to 48 V, RBOOT = 2.2 Ω, ILoad = 5 A 3 t_fallSW_LS0 SW Fall Time at Low Side FET Turn-On LS Turn-On Boost Mode, 48 V to 0 V, RDRV = 0 Ω, ILoad = 5 A 1.5 t_fall (Boost Mode, Hard Switching) SW_LS1 LS Turn-On Boost Mode, 48 V to 0 V, RDRV= 2.2 Ω , ILoad = 5 A 3
Dynamic Characteristics Parameter Definition Figure 3a: Test Circuit for Dynamic Characteristics
VDRV VIN RDRV 100 nF 5 V 1 µF 48 V RDRV VBOOT RBOOT High side VDD RBOOT 2.2 mH input 37.4 Ω (5 V, 50 Ω) HSIN SW 150 Ω 150 Ω 100 nF 47 mF PGND 5 A LSIN 1 kΩ 5 W EN AGND Low side input
EPC23102
37.4 Ω (5 V, 50 Ω) SWa To oscil oscope 150 Ω 150 Ω 50 Ω To To oscil oscope oscil oscope
Figure 3b: Logic Input to Output Switching Node Timing Diagram
2.5 V
HS
50%
IN LS
2.5 V
IN
50% t_delay ~1.46 V HS_off 30 mV
SWa
~0 V -30 mV t_delayLS_off t_delayHS_on t_delayLS_on EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2022 | | 5