Datasheet SA571 (ON Semiconductor) - 8

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SA571 Variable Gain Cell
This equation is linear and temperature−insensitive, but it Figure 12 is a diagram of the variable gain cell. This is a assumes ideal transistors. linearized two−quadrant transconductance multiplier. Q1, If the transistors are not perfectly matched, a parabolic, Q2 and the op amp provide a predistorted drive signal for the non−linearity is generated, which results in second gain control pair, Q3 and Q4. The gain is controlled by IG and harmonic distortion. Figure 13 gives an indication of the a current mirror provides the output current. magnitude of the distortion caused by a given input level and offset voltage. The distortion is linearly proportional to the V+ magnitude of the offset and the input level. Saturation of the gain cell occurs at a +8 dBm level. At a nominal operating I1 140mA level of 0 dBm, a 1.0 mV offset will yield 0.34% of second harmonic distortion. Most circuits are somewhat better than this, which means our overall offsets are typically about mV.
−
The distortion is not affected by the magnitude of the gain
+
control current, and it does not increase as the gain is R2 changed. This second harmonic distortion could be 20k eliminated by making perfect transistors, but since that Q1 Q2 Q3 Q4 V would be difficult, we have had to resort to other methods. IN IIN A trim pin has been provided to allow trimming of the internal offsets to zero, which effectively eliminated second I harmonic distortion. Figure 14 shows the simple trim 2 (= 2I1) IG 280mA network required. V− 4 I I V G G IN NOTE: I + I + OUT I IN I R 1 2 2 3 4mV
Figure 12. Simplified
D
G Cell Schematic
2 3mV % THD 2mV The op amp maintains the base and collector of Q1 at 1 ground potential (V 1mV REF) by controlling the base of Q2. The .34 input current IIN (= VIN/R2) is thus forced to flow through Q −6 0 +6 1 along with the current I1, so IC1 = I1 + IIN. Since I2 has INPUT LEVEL (dBm) been set at twice the value of I1, the current through Q2 is: I
Figure 13.
D
G Cell Distortion vs. Offset Voltage
2 − (I1 + IIN) = I1 − IIN = IC2. The op amp has thus forced a linear current swing between Q1 and Q2 by providing the proper drive to the base of Q2. V This drive signal will be linear for small signals, but very CC non−linear for large signals, since it is compensating for the non−linearity of the differential pair, Q1 and Q2, under large R signal conditions. The key to the circuit is that this same predistorted drive 3.6V signal is applied to the gain control pair, Q 6.2kW 3 and Q4. When two differential pairs of transistors have the same signal 20kW To THD Trim applied, their collector current ratios will be identical ≈200pF regardless of the magnitude of the currents. This gives us: I I I ) I C1 + C4 + 1 IN I I I * I C2 C3 1 IN
Figure 14. THD Trim Network
plus the relationships IG = IC3 + IC4 and IOUT = IC4 − IC3 will yield the multiplier transfer function, I V I I + G I + IN G OUT I IN R I 1 2 1
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