Datasheet AD9625 (Analog Devices) - 9

Data Sheet AD9625 ABSOLUTE MAXIMUM RATINGS Table 6.
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a
Parameter Rating
Electrical stress rating only; functional operation of the product at these AVDD1 to AGND −0.3 V to +1.32 V or any other conditions above those indicated in the operational AVDD2 to AGND −0.3 V to +2.75 V section of this specification is not implied. Operation beyond DRVDD1 to DRGND −0.3 V to +1.32 V the maximum operating conditions for extended periods may DRVDD2 to DRGND −0.3 V to +2.75 V affect product reliability. DVDD1 to DGND −0.3 V to +1.32 V
THERMAL CHARACTERISTICS
DVDD2 to DGND −0.3 V to +2.75 V DVDDIO to DGND −0.3 V to +3.63 V The following characteristics are for a 4-layer and 10-layer SPI_VDDIO to DGND −0.3 V to +3.63 V printed circuit board (PCB). AGND to DRGND −0.3 V to +0.3 V VIN± to AGND −0.3 V to AVDD1 + 0.2 V
Table 7. Thermal Resistance
VCM to AGND −0.3 V to AVDD1 + 0.2 V
θJA ΨJT ΨJB θJC
VMON to AGND −0.3 V to AVDD1 + 0.2 V
PCB TA (°C) (°C/W) (°C/W) (°C/W) (°C/W)
CLK± to AGND −0.3 V to AVDD1 + 0.2 V 4-Layer 85.0 18.7 0.61 6.1 1.4 SYSREF± to AGND −0.3 V to AVDD1 + 0.2 V 10-Layer 85.0 11.5 0.61 4.1 N/A1 SYNCINB± to DRGND −0.3 V to DRVDD2 + 0.2 V 1 N/A means not applicable. SCLK to DRGND −0.3 V to SPI_VDDIO + 0.2 V SDIO to DRGND −0.3 V to SPI_VDDIO + 0.2 V IRQ to DRGND −0.3 V to DVDDIO + 0.2 V
ESD CAUTION
RSTB to DRGND −0.3 V to DVDDIO + 0.2 V CSB to DRGND −0.3 V to SPI_VDDIO + 0.2 V FD to DRGND −0.3 V to DVDDIO + 0.2 V DIVCLK± to DRGND −0.3 V to DRVDD2 + 0.2 V SERDOUT[x]± to DRGND −0.3 V to DRVDD1 + 0.2 V Environmental Storage Temperature Range −60°C to +150°C Operating Case Temperature Range −40°C to +85°C (measured at case) Maximum Junction Temperature 110°C Rev. B | Page 9 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE