Datasheet AD9625 (Analog Devices) - 10

AD9625 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9625 TOP VIEW (Not to Scale) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A AGND AGND AGND AVDD1 AGND AVDD2 VCM AGND VIN+ VIN– AGND VM_BYP AVDD2 AVDD2 B AGND AGND AGND AGND AVDD1 AGND AVDD2 AGND AGND AGND AGND AVDD2 AGND AGND C AGND AGND AGND AGND AGND AVDD1 AGND AVDD2 AGND AGND AVDD2 AGND AGND AVDD1 D DVDD1 DVDD1 DVDD1 DNC AGND AGND AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AVDD1 AVDD1 E DGND DGND DGND DVDD2 VMON AGND AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AGND AGND F DVDD1 DVDD1 DVDD1 SPI_VDDIO DVDDIO AGND AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AGND CLK+ G DGND DGND DGND CSB DVDDIO AGND AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AGND CLK– H DVDD1 DVDD1 DVDD1 SCLK IRQ AGND AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AGND AGND J DGND DGND DGND SDIO FD RBIAS_EXT AVDD1 AVDD2 AGND AGND AVDD2 AVDD1 AGND SYSREF+ K DVDD1 DVDD1 RSTB PWDN AGND AGND AGND AGND AGND AGND AGND AGND AGND SYSREF– L DGND DNC SYNCINB– SYNCINB+ DGND DGND DGND DGND DGND DNC DNC DNC AGND AGND M DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRGND DRVDD1 REXT DRGND DRGND N SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT DRVDD1 DRVDD1 DRVDD1 VP_BYP DRVDD2 DRVDD2 [7]+ [6]+ [5]+ [4]+ [3]+ [2]+ [1]+ [0]+ P SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT SERDOUT DRVDD1 DRVDD1 DRVDD1 DRGND DIVCLK– DIVCLK+ [7]– [6]– [5]– [4]– [3]– [2]– [1]– [0]–
009
NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. LEAVE THIS PIN FLOATING.
1814- 1 Figure 5. Pin Configuration Rev. B | Page 10 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9625-2.0 AD9625-2.5 AD9625-2.6 EQUIVALENT TEST CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE FAST DETECT GAIN THRESHOLD OPERATION Threshold Operation Threshold Format TEST MODES ANALOG INPUT CONSIDERATIONS DIFFERENTIAL INPUT CONFIGURATIONS USING THE ADA4961 DC COUPLING CLOCK INPUT CONSIDERATIONS Clock Jitter Considerations Clock Duty Cycle Considerations DIGITAL DOWNCONVERTERS (DDC) FREQUENCY SYNTHESIZER AND MIXER NUMERICALLY CONTROLLED OSCILLATOR HIGH BANDWIDTH DECIMATOR LOW BANDWIDTH DECIMATOR DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) Data Streaming Link Setup Parameters 8-Bit/10-Bit Encoder Digital Outputs, Timing, and Controls De-Emphasis PHYSICAL LAYER OUTPUT SCRAMBLER TAIL BITS DDC MODES (SINGLE AND DUAL) CHECKSUM 8-BIT/10-BIT ENCODER CONTROL INITIAL LANE ALIGNMENT SEQUENCE (ILAS) LANE SYNCHRONIZATION Multichip Synchronization Using SYSREF± Timestamp Six Lane Output Mode ADC Output Control Bits on JESD204B Samples SYSREF± Setup and Hold IRQ IRQ Guardband Delays (SYSREF± Setup and Hold) Using Rising/Falling Edges of the CLK to Latch SYSREF± Test Modes JESD204B APPLICATION LAYERS fS × 2, fS × 4, fS × 8 Modes FRAME ALIGNMENT CHARACTER INSERTION THERMAL CONSIDERATIONS POWER SUPPLY CONSIDERATIONS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTERS APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS CLOCK STABILITY CONSIDERATIONS SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE