Datasheet ADSP-BF538, ADSP-BF538F (Analog Devices) - 8

link to page 7 link to page 13 link to page 13
ADSP-BF538/ ADSP-BF538F Table 3. System and Core Event Mapping (Continued)
may be read or written while in supervisor mode. General- purpose interrupts can be globally enabled and disabled
Core
with the STI and CLI instructions, respectively.
Event Source Event Name
• CEC interrupt pending register (IPEND) – The IPEND DMA10 Interrupt (SPORT3 Rx) IVG9 register keeps track of all nested events. A set bit in the DMA11 Interrupt (SPORT3 Tx) IVG9 IPEND register indicates the event is currently active or DMA5 Interrupt (SPI0) IVG10 nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. DMA14 Interrupt (SPI1) IVG10 The SIC allows further control of event processing by providing DMA15 Interrupt (SPI2) IVG10 three 32-bit interrupt control and status registers. Each register DMA6 Interrupt (UART0 Rx) IVG10 contains a bit corresponding to each of the peripheral interrupt DMA7 Interrupt (UART0 Tx) IVG10 events shown in Table 3 on Page 7. DMA16 Interrupt (UART1 Rx) IVG10 • SIC interrupt mask registers (SIC_IMASKx) – These regis- DMA17 Interrupt (UART1 Tx) IVG10 ters control the masking and unmasking of each peripheral interrupt event. When a bit is set in these registers, that DMA18 Interrupt (UART2 Rx) IVG10 peripheral event is unmasked and will be processed by the DMA19 Interrupt (UART2 Tx) IVG10 system when asserted. A cleared bit in these registers masks Timer0, Timer1, Timer2 Interrupts IVG11 the peripheral event, preventing the processor from servic- TWI0 Interrupt IVG11 ing the event. TWI1 Interrupt IVG11 • SIC interrupt status registers (SIC_ISRx) – As multiple peripherals can be mapped to a single event, these registers CAN Receive Interrupt IVG11 allow the software to determine which peripheral event CAN Transmit Interrupt IVG11 source triggered the interrupt. A set bit indicates the Port F GPIO Interrupts A and B IVG12 peripheral is asserting the interrupt, and a cleared bit indi- MDMA0 Stream 0 Interrupt IVG13 cates the peripheral is not asserting the event. MDMA0 Stream 1 Interrupt IVG13 • SIC interrupt wake-up enable registers (SIC_IWRx) – By enabling the corresponding bit in these registers, a periph- MDMA1 Stream 0 Interrupt IVG13 eral can be configured to wake up the processor, should the MDMA1 Stream 1 Interrupt IVG13 core be idled or in sleep mode when the event is generated. Software Watchdog Timer IVG13 (For more information, see Dynamic Power Management on Page 13.)
Event Control
Because multiple interrupt sources can map to a single general- The ADSP-BF538/ADSP-BF538F processors provide the user purpose interrupt, multiple pulse assertions can occur simulta- with a very flexible mechanism to control the processing of neously, before or during interrupt processing for an interrupt events. In the CEC, three registers are used to coordinate and event already detected on this interrupt input. The IPEND control events. Each register is 32 bits wide: register contents are monitored by the SICs as the interrupt acknowledgement. • CEC interrupt latch register (ILAT) – The ILAT register indicates when events have been latched. The appropriate The appropriate ILAT register bit is set when an interrupt rising bit is set when the processor has latched the event and edge is detected (detection requires two core clock cycles). The cleared when the event has been accepted into the system. bit is cleared when the respective IPEND register bit is set. The This register is updated automatically by the controller, but IPEND bit indicates that the event has entered into the proces- it may also be written to clear (cancel) latched events. This sor pipeline. At this point the CEC will recognize and queue the register may be read while in supervisor mode and may next rising edge event on the corresponding event input. The only be written while in supervisor mode when the corre- minimum latency from the rising edge transition of the general- sponding IMASK bit is cleared. purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depend- • CEC interrupt mask register (IMASK) – The IMASK regis- ing on the activity within and the state of the processor. ter controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is
DMA CONTROLLERS
unmasked and will be processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, pre- The ADSP-BF538/ADSP-BF538F processors have two, inde- venting the processor from servicing the event even though pendent DMA controllers that support automated data transfers the event may be latched in the ILAT register. This register with minimal overhead for the processor core. DMA transfers can occur between the processor internal memories and any of its DMA capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA capable peripherals and external devices connected to the external memory inter- Rev. E | Page 8 of 60 | November 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF538F8 Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide