Datasheet ADSP-BF538, ADSP-BF538F (Analog Devices) - 7

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ADSP-BF538/ ADSP-BF538F
ensures that servicing of a higher priority event takes prece-
Table 2. Core Event Controller (CEC)
dence over servicing of a lower priority event. The controller provides support for five different types of events:
Priority (0 is Highest) Event Class EVT Entry
• Emulation – An emulation event causes the processor to enter emulation mode, allowing command and control of 0 Em ulation/Test Control EMU the processor via the JTAG interface. 1 Reset RST • Reset – This event resets the processor. 2 Nonmaskable Interrupt NMI • Nonmaskable interrupt (NMI) – The NMI event can be 3 Exception EVX generated by the software watchdog timer or by the NMI 4 Reserved — input signal to the processor. The NMI event is frequently 5 Hardware Error IVHW used as a power-down indicator to initiate an orderly shut- down of the system. 6 Core Timer IVTMR 7 General Interrupt 7 IVG7 • Exceptions – Events that occur synchronously to program flow (the exception is taken before the instruction is 8 General Interrupt 8 IVG8 allowed to complete). Conditions such as data alignment 9 General Interrupt 9 IVG9 violations and undefined instructions cause exceptions. 10 General Interrupt 10 IVG10 • Interrupts – Events that occur asynchronously to program 11 General Interrupt 11 IVG11 flow. They are caused by input pins, timers, and other 12 General Interrupt 12 IVG12 peripherals, as well as by an explicit software instruction. 13 General Interrupt 13 IVG13 Each event type has an associated register to hold the return address and an associated return-from-event instruction. When 14 General Interrupt 14 IVG14 an event is triggered, the state of the processors is saved on the 15 General Interrupt 15 IVG15 supervisor stack. The ADSP-BF538/ADSP-BF538F processors’ event controllers
Table 3. System and Core Event Mapping
consist of two stages, the core event controller (CEC) and the
Core
system interrupt controller (SIC). The core event controller
Event Source Event Name
works with the system interrupt controller to prioritize and con- trol all system events. Conceptually, interrupts from the PLL Wake-Up Interrupt IVG7 peripherals enter into the SIC and are then routed directly into DMA Controller 0 Error IVG7 the general-purpose interrupts of the CEC. DMA Controller 1 Error IVG7
Core Event Controller (CEC)
PPI Error Interrupt IVG7 The CEC supports nine general-purpose interrupts (IVG15–7), SPORT0 Error Interrupt IVG7 in addition to the dedicated interrupt and exception events. Of SPORT1 Error Interrupt IVG7 these general-purpose interrupts, the two lowest priority inter- SPORT2 Error Interrupt IVG7 rupts (IVG15–14) are recommended to be reserved for software SPORT3 Error Interrupt IVG7 interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the processor. SPI0 Error Interrupt IVG7 Table 2 describes the inputs to the CEC, identifies their names SPI1 Error Interrupt IVG7 in the event vector table (EVT), and lists their priorities. SPI2 Error Interrupt IVG7
System Interrupt Controller (SIC)
UART0 Error Interrupt IVG7 UART1 Error Interrupt IVG7 The system interrupt controllers (SIC) provides the mapping and routing of events from the many peripheral interrupt UART2 Error Interrupt IVG7 sources to the prioritized general-purpose interrupt inputs of CAN Error Interrupt IVG7 the CEC. Although the ADSP-BF538/ADSP-BF538F processors Real-Time Clock Interrupts IVG8 provide a default mapping, programs can alter the mappings DMA0 Interrupt (PPI) IVG8 and priorities of interrupt events by writing the appropriate val- ues into the interrupt assignment registers (SIC_IARx). DMA1 Interrupt (SPORT0 Rx) IVG9 Table 3 describes the inputs into the SIC and the default map- DMA2 Interrupt (SPORT0 Tx) IVG9 pings into the CEC. DMA3 Interrupt (SPORT1 Rx) IVG9 DMA4 Interrupt (SPORT1 Tx) IVG9 DMA8 Interrupt (SPORT2 Rx) IVG9 DMA9 Interrupt (SPORT2 Tx) IVG9 Rev. E | Page 7 of 60 | November 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Low Power Architecture System Integration ADSP-BF538/ADSP-BF538F Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory Flash Memory (ADSP-BF538F8 Only) Flash Memory Programming Flash Memory Sector Protection I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Ports 2-Wire Interface UART Ports General-Purpose Ports Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Controller Area Network (CAN) Interface Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Ports—Master Timing Serial Peripheral Interface Ports—Slave Timing General-Purpose Port Timing Timer Clock Timing Timer Cycle Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing JTAG Test and Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 316-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Ordering Guide