Datasheet AD73322L (Analog Devices) - 2
| 制造商 | Analog Devices |
| 描述 | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| 页数 / 页 | 48 / 2 — AD73322L. TABLE OF CONTENTS |
| 修订版 | A |
| 文件格式/大小 | PDF / 1.2 Mb |
| 文件语言 | 英语 |
AD73322L. TABLE OF CONTENTS
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AD73322L TABLE OF CONTENTS
Specifications... 4 Sample Rate Divider... 19 Current Summary... 6 DAC Advance Register .. 20 Signal Ranges .. 7 Control Register A ... 21 Timing Characteristics .. 7 Control Register B.. 21 Timing Diagrams.. 8 Control Register C.. 21 Absolute Maximum Ratings.. 9 Control Register D ... 22 ESD Caution.. 9 Control Register E .. 22 Pin Configurations and Function Descriptions ... 10 Control Register F .. 22 Terminology .. 12 Control Register G ... 23 Abbreviations .. 12 Control Register H ... 23 Typical Performance Characteristics and Functional Block Operation... 24 Diagram ... 13 Resetting the AD73322L ... 24 Functional Descriptions .. 14 Power Management ... 24 Encoder Channels .. 14 Operating Modes.. 24 Programmable Gain Amplifier... 14 Program (Control) Mode .. 24 ADC ... 14 Data Mode... 25 Analog Sigma-Delta Modulator ... 14 Mixed Program/Data Mode.. 25 Decimation Filter.. 15 Digital Loop-Back Mode... 25 ADC Coding ... 15 SPORT Loop-Back Mode.. 25 Decoder Channel.. 16 Analog Loop-Back Mode .. 26 DAC Coding.. 16 Interfacing ... 27 Interpolation Filter ... 16 Cascade Operation... 27 Analog Smoothing Filter and PGA.. 16 Performance .. 29 Differential Output Amplifiers ... 16 Encoder Section.. 29 Voltage Reference ... 16 Encoder Group Delay .. 30 Analog and Digital Gain Taps... 17 Decoder Section ... 30 Digital Gain Tap.. 18 On-Chip Filtering... 31 Serial Port (SPORT) ... 18 Decoder Group Delay.. 31 SPORT Overview.. 18 Design Considerations... 32 SPORT Register Maps.. 19 Analog Inputs ... 32 Master Clock Divider... 19 Interfacing to an Electret Microphone .. 34 Serial Clock Rate Divider .. 19 Rev. A | Page 2 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS CURRENT SUMMARY SIGNAL RANGES TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY ABBREVIATIONS TYPICAL PERFORMANCE CHARACTERISTICS AND FUNCTIONAL BLOCK DIA FUNCTIONAL DESCRIPTIONS ENCODER CHANNELS PROGRAMMABLE GAIN AMPLIFIER ADC ANALOG SIGMA-DELTA MODULATOR DECIMATION FILTER ADC CODING DECODER CHANNEL DAC CODING INTERPOLATION FILTER ANALOG SMOOTHING FILTER AND PGA DIFFERENTIAL OUTPUT AMPLIFIERS VOLTAGE REFERENCE ANALOG AND DIGITAL GAIN TAPS DIGITAL GAIN TAP SERIAL PORT (SPORT) SPORT OVERVIEW SPORT REGISTER MAPS MASTER CLOCK DIVIDER SERIAL CLOCK RATE DIVIDER SAMPLE RATE DIVIDER DAC ADVANCE REGISTER CONTROL REGISTER A CONTROL REGISTER B CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E CONTROL REGISTER F CONTROL REGISTER G CONTROL REGISTER H OPERATION RESETTING THE AD73322L POWER MANAGEMENT OPERATING MODES PROGRAM (CONTROL) MODE DATA MODE MIXED PROGRAM/DATA MODE DIGITAL LOOP-BACK MODE SPORT LOOP-BACK MODE ANALOG LOOP-BACK MODE INTERFACING CASCADE OPERATION PERFORMANCE ENCODER SECTION ENCODER GROUP DELAY DECODER SECTION ON-CHIP FILTERING DECODER GROUP DELAY DESIGN CONSIDERATIONS ANALOG INPUTS INTERFACING TO AN ELECTRET MICROPHONE ANALOG OUTPUT DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT DIGITAL INTERFACING CASCADE OPERATION GROUNDING AND LAYOUT DSP PROGRAMMING CONSIDERATIONS DSP SPORT CONFIGURATION DSP SPORT INTERRUPTS DSP SOFTWARE CONSIDERATIONS WHEN INTERFACING TO THE AD73322L OPERATING MODE MIXED-MODE OPERATION INTERRUPTS INITIALIZATION RUNNING THE AD73322L WITH ADCS OR DACS IN POWER-DOWN DAC TIMING CONTROL EXAMPLE CONFIGURING AN AD73322L TO OPERATE IN DATA MODE CONFIGURING AN AD73322L TO OPERATE IN MIXED MODE OUTLINE DIMENSIONS ORDERING GUIDE
AD73322L TABLE OF CONTENTS
Specifications... 4 Sample Rate Divider... 19 Current Summary... 6 DAC Advance Register .. 20 Signal Ranges .. 7 Control Register A ... 21 Timing Characteristics .. 7 Control Register B.. 21 Timing Diagrams.. 8 Control Register C.. 21 Absolute Maximum Ratings.. 9 Control Register D ... 22 ESD Caution.. 9 Control Register E .. 22 Pin Configurations and Function Descriptions ... 10 Control Register F .. 22 Terminology .. 12 Control Register G ... 23 Abbreviations .. 12 Control Register H ... 23 Typical Performance Characteristics and Functional Block Operation... 24 Diagram ... 13 Resetting the AD73322L ... 24 Functional Descriptions .. 14 Power Management ... 24 Encoder Channels .. 14 Operating Modes.. 24 Programmable Gain Amplifier... 14 Program (Control) Mode .. 24 ADC ... 14 Data Mode... 25 Analog Sigma-Delta Modulator ... 14 Mixed Program/Data Mode.. 25 Decimation Filter.. 15 Digital Loop-Back Mode... 25 ADC Coding ... 15 SPORT Loop-Back Mode.. 25 Decoder Channel.. 16 Analog Loop-Back Mode .. 26 DAC Coding.. 16 Interfacing ... 27 Interpolation Filter ... 16 Cascade Operation... 27 Analog Smoothing Filter and PGA.. 16 Performance .. 29 Differential Output Amplifiers ... 16 Encoder Section.. 29 Voltage Reference ... 16 Encoder Group Delay .. 30 Analog and Digital Gain Taps... 17 Decoder Section ... 30 Digital Gain Tap.. 18 On-Chip Filtering... 31 Serial Port (SPORT) ... 18 Decoder Group Delay.. 31 SPORT Overview.. 18 Design Considerations... 32 SPORT Register Maps.. 19 Analog Inputs ... 32 Master Clock Divider... 19 Interfacing to an Electret Microphone .. 34 Serial Clock Rate Divider .. 19 Rev. A | Page 2 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS CURRENT SUMMARY SIGNAL RANGES TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY ABBREVIATIONS TYPICAL PERFORMANCE CHARACTERISTICS AND FUNCTIONAL BLOCK DIA FUNCTIONAL DESCRIPTIONS ENCODER CHANNELS PROGRAMMABLE GAIN AMPLIFIER ADC ANALOG SIGMA-DELTA MODULATOR DECIMATION FILTER ADC CODING DECODER CHANNEL DAC CODING INTERPOLATION FILTER ANALOG SMOOTHING FILTER AND PGA DIFFERENTIAL OUTPUT AMPLIFIERS VOLTAGE REFERENCE ANALOG AND DIGITAL GAIN TAPS DIGITAL GAIN TAP SERIAL PORT (SPORT) SPORT OVERVIEW SPORT REGISTER MAPS MASTER CLOCK DIVIDER SERIAL CLOCK RATE DIVIDER SAMPLE RATE DIVIDER DAC ADVANCE REGISTER CONTROL REGISTER A CONTROL REGISTER B CONTROL REGISTER C CONTROL REGISTER D CONTROL REGISTER E CONTROL REGISTER F CONTROL REGISTER G CONTROL REGISTER H OPERATION RESETTING THE AD73322L POWER MANAGEMENT OPERATING MODES PROGRAM (CONTROL) MODE DATA MODE MIXED PROGRAM/DATA MODE DIGITAL LOOP-BACK MODE SPORT LOOP-BACK MODE ANALOG LOOP-BACK MODE INTERFACING CASCADE OPERATION PERFORMANCE ENCODER SECTION ENCODER GROUP DELAY DECODER SECTION ON-CHIP FILTERING DECODER GROUP DELAY DESIGN CONSIDERATIONS ANALOG INPUTS INTERFACING TO AN ELECTRET MICROPHONE ANALOG OUTPUT DIFFERENTIAL-TO-SINGLE-ENDED OUTPUT DIGITAL INTERFACING CASCADE OPERATION GROUNDING AND LAYOUT DSP PROGRAMMING CONSIDERATIONS DSP SPORT CONFIGURATION DSP SPORT INTERRUPTS DSP SOFTWARE CONSIDERATIONS WHEN INTERFACING TO THE AD73322L OPERATING MODE MIXED-MODE OPERATION INTERRUPTS INITIALIZATION RUNNING THE AD73322L WITH ADCS OR DACS IN POWER-DOWN DAC TIMING CONTROL EXAMPLE CONFIGURING AN AD73322L TO OPERATE IN DATA MODE CONFIGURING AN AD73322L TO OPERATE IN MIXED MODE OUTLINE DIMENSIONS ORDERING GUIDE