Datasheet BUK7V4R2-40H (Nexperia) - 8
| 制造商 | Nexperia |
| 描述 | Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration) |
| 页数 / 页 | 13 / 8 — Nexperia. BUK7V4R2-40H. Dual N-channel 40 V, 4.2 mOhm standard level … |
| 修订版 | 11022021 |
| 文件格式/大小 | PDF / 313 Kb |
| 文件语言 | 英语 |
Nexperia. BUK7V4R2-40H. Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
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Nexperia BUK7V4R2-40H Dual N-channel 40 V, 4.2 mOhm standard level MOSFET in LFPAK56D (half-bridge configuration)
aaa-032388 2.4 aaa-032389 10 a VGS (V ( ) V 8 1.8 6 1.2 32 3 2 V 4 VDS = 1 4 1 4 V 0.6 2 0 0 -60 -30 0 30 60 90 120 150 180 0 4 8 12 16 20 24 28 32 Tj (°C) QG (nC) Tj = 25 °C; ID = 20 A
Fig. 13. Gate-source voltage as a function of gate Fig. 12. Normalized drain-source on-state resistance charge; typical values, FET1 and FET2 factor as a function of junction temperature, FET1 and FET2
aaa-032390 104 V C DS (p ( F p ) ID Ciss 103 C V oss o GS(pl) VGS(th) 102 Crss VGS QGS2 QGS1 10 QGS QGD 10-1 1 10 102 Q V G(tot) DS (V) 003aaa508 VGS = 0 V; f = 1 MHz
Fig. 14. Gate charge waveform definitions Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values, FET1 and FET2
BUK7V4R2-40H All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. Al rights reserved
Product data sheet 11 February 2021 8 / 13
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Quick reference data 5. Pinning information 6. Ordering information 7. Marking 8. Limiting values 9. Thermal characteristics 10. Characteristics 11. Package outline 12. Soldering 13. Legal information Contents
aaa-032388 2.4 aaa-032389 10 a VGS (V ( ) V 8 1.8 6 1.2 32 3 2 V 4 VDS = 1 4 1 4 V 0.6 2 0 0 -60 -30 0 30 60 90 120 150 180 0 4 8 12 16 20 24 28 32 Tj (°C) QG (nC) Tj = 25 °C; ID = 20 A
Fig. 13. Gate-source voltage as a function of gate Fig. 12. Normalized drain-source on-state resistance charge; typical values, FET1 and FET2 factor as a function of junction temperature, FET1 and FET2
aaa-032390 104 V C DS (p ( F p ) ID Ciss 103 C V oss o GS(pl) VGS(th) 102 Crss VGS QGS2 QGS1 10 QGS QGD 10-1 1 10 102 Q V G(tot) DS (V) 003aaa508 VGS = 0 V; f = 1 MHz
Fig. 14. Gate charge waveform definitions Fig. 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values, FET1 and FET2
BUK7V4R2-40H All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. Al rights reserved
Product data sheet 11 February 2021 8 / 13
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Quick reference data 5. Pinning information 6. Ordering information 7. Marking 8. Limiting values 9. Thermal characteristics 10. Characteristics 11. Package outline 12. Soldering 13. Legal information Contents