Datasheet STGAP2SICS (STMicroelectronics) - 3

link to page 3 link to page 3
STGAP2SICS Pin description and connection diagram 2 Pin description and connection diagram Figure 3. Pin connection (top view) - Single output and Miller CLAMP option
VDD 1 8 GNDISO IN+ 2 7 CLAMP IN- 3 6 GOUT GND 4 5 VH
Figure 4. Pin connection (top view) - Separated outputs option
VDD 1 8 GNDISO IN+ 2 7 GOFF IN- 3 6 GON GND 4 5 VH
Table 1. Pin Description Pin # Pin Name Type Function Figure 4 Figure 3
1 1 VDD Power Supply Driver logic supply voltage. 2 2 IN+ Logic Input Driver logic input, active high. 3 3 IN- Logic Input Driver logic input, active low. 4 4 GND Power Supply Driver logic ground. 5 5 VH Power Supply Gate driving positive voltage supply. - 6 GOUT Analog Output Sink/Source output. - 7 CLAMP Analog Output Active Miller Clamp. 6 - GON Analog Output Source output. 7 - GOFF Analog Output Sink output. 8 8 GNDISO Power Supply Gate driving Isolated ground.
DS13402
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Rev 1 page 3/24
Document Outline Cover image Product status link / summary Features Application Description 1 Block diagram 2 Pin description and connection diagram 3 Electrical data 3.1 Absolute maximum ratings 3.2 Thermal data 3.3 Recommended operating conditions 4 Electrical characteristics 5 Isolation 6 Functional description 6.1 Gate driving power supply and UVLO 6.2 Power-up, power-down and “safe state” 6.3 Control inputs 6.4 Miller Clamp function 6.5 Watchdog 6.6 Thermal shutdown protection 6.7 Standby function 7 Typical application diagram 8 Layout 8.1 Layout guidelines and considerations 8.2 Layout example 9 Testing and characterization information 10 Package information 10.1 SO-8W package information 10.2 SO-8W suggested land pattern 11 Ordering information Revision history Contents List of tables List of figures