Datasheet OPA205, OPA2205, OPA4205 (Texas Instruments) - 4
| 制造商 | Texas Instruments |
| 描述 | Dual, rail-to-rail bipolar precision e-trim op amp with low input bias current and low noise |
| 页数 / 页 | 47 / 4 — OPA205, OP. A2205, OP. A4205. www.ti.com. 5 Pin Configuration and … |
| 文件格式/大小 | PDF / 3.0 Mb |
| 文件语言 | 英语 |
OPA205, OP. A2205, OP. A4205. www.ti.com. 5 Pin Configuration and Functions. Figure 5-1. OPA205 D Package, 8-Pin SOIC (Top View)
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OPA205, OP A2205, OP A4205
SBOS962F – APRIL 2020 – REVISED MARCH 2023
www.ti.com 5 Pin Configuration and Functions
NC 1 8 NC 2 ±IN ± 7 V+ +IN 3 + 6 OUT V 4 ± 5 NC Not to scale
Figure 5-1. OPA205 D Package, 8-Pin SOIC (Top View) Table 5-1. Pin Functions: OPA205 PIN TYPE DESCRIPTION NAME NO.
+IN 3 Input Noninverting input –IN 2 Input Inverting input NC 1, 5, 8 — No internal connection (can be left floating) OUT 6 Output Output V+ 7 — Positive (highest) power supply V– 4 — Negative (lowest) power supply OUT A 1 8 V+ 2 ±IN A 7 OUT B +IN A 3 6 ±IN B V 4 ± 5 +IN B Not to scale
Figure 5-2. OPA2205 DGK Package, 8-Pin VSSOP and D Package, 8-pin SOIC (Top View) Table 5-2. Pin Functions: OPA2205 PIN TYPE DESCRIPTION NAME NO.
+IN A 3 Input Noninverting input, channel A –IN A 2 Input Inverting input, channel A +IN B 5 Input Noninverting input, channel B –IN B 6 Input Inverting input, channel B OUT A 1 Output Output, channel A OUT B 7 Output Output, channel B V+ 8 — Positive (highest) power supply V– 4 — Negative (lowest) power supply 4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: OPA205 OPA2205 OPA4205 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information: OPA205 6.5 Thermal Information: OPA2205 6.6 Thermal Information: OPA4205 6.7 Electrical Characteristics: VS = ±5 V 6.8 Electrical Characteristics: VS = ±15 V 6.9 Typical Characteristics 7 Parameter Measurement Information 7.1 Typical Specifications and Distributions 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Input Offset Trimming 8.3.2 Lower Input Bias With Super-Beta Inputs 8.3.3 Overload Power Limiter 8.3.4 EMI Rejection 8.4 Device Functional Modes 9 Application and Implementation 9.1 Application Information 9.2 Typical Applications 9.2.1 High-Precision Signal-Chain Input Buffer 9.2.1.1 Design Requirements 9.2.1.2 Detailed Design Procedure 9.2.1.3 Application Curves 9.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier 9.2.3 Second-Order Low-Pass Filter 9.3 Power Supply Recommendations 9.4 Layout 9.4.1 Layout Guidelines 9.4.2 Layout Example 10 Device and Documentation Support 10.1 Device Support 10.1.1 Development Support 10.1.1.1 PSpice® for TI 10.2 Documentation Support 10.2.1 Related Documentation 10.3 Receiving Notification of Documentation Updates 10.4 Support Resources 10.5 Trademarks 10.6 Electrostatic Discharge Caution 10.7 Glossary 11 Mechanical, Packaging, and Orderable Information
SBOS962F – APRIL 2020 – REVISED MARCH 2023
www.ti.com 5 Pin Configuration and Functions
NC 1 8 NC 2 ±IN ± 7 V+ +IN 3 + 6 OUT V 4 ± 5 NC Not to scale
Figure 5-1. OPA205 D Package, 8-Pin SOIC (Top View) Table 5-1. Pin Functions: OPA205 PIN TYPE DESCRIPTION NAME NO.
+IN 3 Input Noninverting input –IN 2 Input Inverting input NC 1, 5, 8 — No internal connection (can be left floating) OUT 6 Output Output V+ 7 — Positive (highest) power supply V– 4 — Negative (lowest) power supply OUT A 1 8 V+ 2 ±IN A 7 OUT B +IN A 3 6 ±IN B V 4 ± 5 +IN B Not to scale
Figure 5-2. OPA2205 DGK Package, 8-Pin VSSOP and D Package, 8-pin SOIC (Top View) Table 5-2. Pin Functions: OPA2205 PIN TYPE DESCRIPTION NAME NO.
+IN A 3 Input Noninverting input, channel A –IN A 2 Input Inverting input, channel A +IN B 5 Input Noninverting input, channel B –IN B 6 Input Inverting input, channel B OUT A 1 Output Output, channel A OUT B 7 Output Output, channel B V+ 8 — Positive (highest) power supply V– 4 — Negative (lowest) power supply 4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: OPA205 OPA2205 OPA4205 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information: OPA205 6.5 Thermal Information: OPA2205 6.6 Thermal Information: OPA4205 6.7 Electrical Characteristics: VS = ±5 V 6.8 Electrical Characteristics: VS = ±15 V 6.9 Typical Characteristics 7 Parameter Measurement Information 7.1 Typical Specifications and Distributions 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Input Offset Trimming 8.3.2 Lower Input Bias With Super-Beta Inputs 8.3.3 Overload Power Limiter 8.3.4 EMI Rejection 8.4 Device Functional Modes 9 Application and Implementation 9.1 Application Information 9.2 Typical Applications 9.2.1 High-Precision Signal-Chain Input Buffer 9.2.1.1 Design Requirements 9.2.1.2 Detailed Design Procedure 9.2.1.3 Application Curves 9.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier 9.2.3 Second-Order Low-Pass Filter 9.3 Power Supply Recommendations 9.4 Layout 9.4.1 Layout Guidelines 9.4.2 Layout Example 10 Device and Documentation Support 10.1 Device Support 10.1.1 Development Support 10.1.1.1 PSpice® for TI 10.2 Documentation Support 10.2.1 Related Documentation 10.3 Receiving Notification of Documentation Updates 10.4 Support Resources 10.5 Trademarks 10.6 Electrostatic Discharge Caution 10.7 Glossary 11 Mechanical, Packaging, and Orderable Information