Datasheet AD8422 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | High Performance, Low Power, Rail-to-Rail Precision Instrumentation Amplifier |
| 页数 / 页 | 24 / 10 — AD8422. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 400. 350. 300. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 655 Kb |
| 文件语言 | 英语 |
AD8422. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 400. 350. 300. 250. S T. T 200. 200. 150. 100. –90. –60. –30. –300. –200. –100
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AD8422 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
T = 25°C, VS = ±15, VREF = 0 V, RL = 10 kΩ, unless otherwise noted.
400 400 350 350 300 300 250 250 S T S HI T 200 200 HI 150 150 100 100 50 50 0 0 –90 –60 –30 0 30 60 90
03 0
–300 –200 –100 0 100 200 300
97- -006
INPUT OFFSET VOLTAGE (µV)
97 111
OUTPUT OFFSET VOLTAGE (µV)
111 Figure 4. Typical Distribution of Input Offset Voltage Figure 7. Typical Distribution of Output Offset Voltage
800 400 600 300 S T S T HI HI 400 200 200 100 0 0 –900 –600 –300 0 300 600 900
040
–300 –200 –100 0 100 200 300
7- -007
POSITIVE INPUT BIAS CURRENT (pA)
97 119
INPUT OFFSET CURRENT (pA)
1 111 Figure 5. Typical Distribution of Input Bias Current Figure 8. Typical Distribution of Input Offset Current
500 500 400 400 S 300 T S HI 300 T HI 200 200 100 100 0 0
05 8
–9 –6 –3 0 3 6 9
0
–40 –20 0 20 40
-00 97- 7
PSRR G = 1 (µV/V)
19 111
CMRR G = 1 (µV/V)
11 Figure 6. Typical Distribution of PSRR (G = 1) Figure 9. Typical Distribution of CMRR (G = 1) Rev. A | Page 10 of 24 Document Outline FEATURES APPLICATIONS CONNECTION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS SOIC PACKAGE MSOP PACKAGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARCHITECTURE GAIN SELECTION RG Power Dissipation REFERENCE TERMINAL INPUT VOLTAGE RANGE LAYOUT Common-Mode Rejection Ratio over Frequency Power Supplies and Grounding Reference Pin INPUT BIAS CURRENT RETURN PATH INPUT VOLTAGES BEYOND THE SUPPLY RAILS Input Voltages Beyond the Maximum Ratings RADIO FREQUENCY INTERFERENCE (RFI) APPLICATIONS INFORMATION PRECISION BRIDGE CONDITIONING PROCESS CONTROL ANALOG INPUT OUTLINE DIMENSIONS ORDERING GUIDE
T = 25°C, VS = ±15, VREF = 0 V, RL = 10 kΩ, unless otherwise noted.
400 400 350 350 300 300 250 250 S T S HI T 200 200 HI 150 150 100 100 50 50 0 0 –90 –60 –30 0 30 60 90
03 0
–300 –200 –100 0 100 200 300
97- -006
INPUT OFFSET VOLTAGE (µV)
97 111
OUTPUT OFFSET VOLTAGE (µV)
111 Figure 4. Typical Distribution of Input Offset Voltage Figure 7. Typical Distribution of Output Offset Voltage
800 400 600 300 S T S T HI HI 400 200 200 100 0 0 –900 –600 –300 0 300 600 900
040
–300 –200 –100 0 100 200 300
7- -007
POSITIVE INPUT BIAS CURRENT (pA)
97 119
INPUT OFFSET CURRENT (pA)
1 111 Figure 5. Typical Distribution of Input Bias Current Figure 8. Typical Distribution of Input Offset Current
500 500 400 400 S 300 T S HI 300 T HI 200 200 100 100 0 0
05 8
–9 –6 –3 0 3 6 9
0
–40 –20 0 20 40
-00 97- 7
PSRR G = 1 (µV/V)
19 111
CMRR G = 1 (µV/V)
11 Figure 6. Typical Distribution of PSRR (G = 1) Figure 9. Typical Distribution of CMRR (G = 1) Rev. A | Page 10 of 24 Document Outline FEATURES APPLICATIONS CONNECTION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS SOIC PACKAGE MSOP PACKAGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ARCHITECTURE GAIN SELECTION RG Power Dissipation REFERENCE TERMINAL INPUT VOLTAGE RANGE LAYOUT Common-Mode Rejection Ratio over Frequency Power Supplies and Grounding Reference Pin INPUT BIAS CURRENT RETURN PATH INPUT VOLTAGES BEYOND THE SUPPLY RAILS Input Voltages Beyond the Maximum Ratings RADIO FREQUENCY INTERFERENCE (RFI) APPLICATIONS INFORMATION PRECISION BRIDGE CONDITIONING PROCESS CONTROL ANALOG INPUT OUTLINE DIMENSIONS ORDERING GUIDE